Reconfiguration requirements for high speed wireless communication systems

Pionteck, Thilo; Kabulepa, Lukusa D.; Schlachta, Clemens; Glesner, Manfred

doi:10.1109/fpt.2003.1275739

Cited by 5 publications

(6 citation statements)

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“…Pionteck et al [67] note that changing specifications of the MAC layers results in that reconfiguration is required for this layer, yet because power consumption and area overhead are important, more function-specific reconfigurable architectures should be used for the consumer market (as opposed to more general-purpose reconfigurable architectures for the infrastructure market).…”

Section: Chapter 2 Backgroundmentioning

confidence: 99%

“…Consumer devices are typically more power and cost sensitive, and have shorter life, than infras-tructure devices. According to [67], the infrastructure market is better suited for general-purpose reconfigurable hardware devices, while in the consumer market more function-specific reconfigurable architectures may be employed successfully.…”

Section: Scopementioning

confidence: 99%

“…Reconfigurable hardware has therefore potential application in the MAC layer as well. In fact Pionteck et al [67] consider the MAC layer the more suitable layer for using reconfigurable logic.…”

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confidence: 99%

“…Such overheads are not feasible in the context of power-sensitive hand-held devices. Also, only data-flow dominated operations can be efficiently implemented on reconfigurable hardware [67]. The MAC layer has considerable control logic, and it cannot fully exploit the parallelism offered by FPGAs.…”

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A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

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Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.http://theses.gla.ac.uk/865/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study, without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Copyright c Syed Waqar Nabi October 2008In the name of Allah, the Beneficent, the Merciful.Read: In the name of thy Lord Who createth, Createth man from a clot. Read: And thy Lord is the Most Bounteous, Who teacheth by the pen, Teacheth man that which he knew not. Nay, but verily man is rebellious That he thinketh himself independent! Lo! unto thy Lord is the return.The Quran; Chapter 96, Verses 1-7 i Abstract DRMP, a Dynamically Reconfigurable MAC Processor, is an innovative, dynamically reconfigurable System-on-Chip architecture. The architecture exploits substantial overlaps in the functionality of different wireless MAC layers. Its flexibility is specialized for addressing the requirements of the MAC layer of wireless standards. It is targeted at consumer, multi-standard, handheld devices, and its design is meant to address the balance of flexibility and power-efficiency that this target market demands. The DRMP reconfigures packet-by-packet on the fly, allowing execution of concurrent protocol modes on a single hardware co-processor. An interrupt-driven programming model has also been presented and shown to implement the protocol state-machine of the three protocols on a CPU. These features will allow the DRMP to replace three MAC processors in a hand-held device. The most innovative component of the DRMP architecture is its Interface and Reconfiguration Controller. It uses a combination of asynchronous controllers to dynamically reconfigure the functional units in the architecture and delegate MAC tasks to them. The architecture has been modeled in Simulink at cycle-approximate abstraction. Results of simulations involving transmission and reception of packets have been presented, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Its heterogeneous and coarse-grained functional units, limited connectivity requirements between these units, and proportionally large time that these resources are idle, promise a very modest power-consumption, suitable for mobile devices, while offering flexibility to implement different MAC protocols. The Institute of System Level Integration in general, the EngD center and Sian Williams in particular, deserve a special t...

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A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

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“…The hardware system of the processor is built by the Platform Studio work platform of Xilinx Corporation. After that, it is necessary to generate netlist, and then call the netlist in PlanAhead to reconfigure [9].The processor system control and management center is a soft core embedded processor MicroBlaze (MB), it has the advantages of high running speed, less resource, highly configurable, can work together to complete the design of system on programmable chip and other peripheral IP core, widely used in communications, military, and other areas of high-end consumer market. MicroBlaze processor using RISC （Reduced Instruction Set Computer）instruction set architecture and Harvard memory architecture, instruction, data bus width is 32.…”

Section: Advances In Computer Science Research (Acsr) Volume 73mentioning

confidence: 99%