Redesigning commercial floating-gate memory for analog computing applications

Bayat, F. Merrikh; Guo, Xin; Om'mani, H.A.; Do, Nhan; Likharev, K. K.; Strukov, Dmitri B.

doi:10.1109/iscas.2015.7169048

Cited by 34 publications

(20 citation statements)

References 21 publications

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“…2b, by connecting the erase gates of all cells of one column with an additional line, while eliminating the row lines connecting these gates. (Note that this redesign is different from the one performed by our group earlier [8] with the 180 nm ESF1 technology, because of a different structure of its supercells. )…”

Section: B Array Modification and Cell Tuningmentioning

confidence: 88%

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Guo

Bayat

Prezioso

et al. 2017

2017 IEEE Custom Integrated Circuits Conference (CICC)

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We have fabricated and successfully tested an analog vector-by-matrix multiplier, based on redesigned 10×12 arrays of 55 nm commercial NOR flash memory cells. The modified arrays enable high-precision individual analog tuning of each cell, with sub-1% accuracy, while keeping the highly optimized cells, with their long-term state retention, intact. The array has an area of 0.33 μm 2 per cell, and is at least one order of magnitude more dense than the reported prior implementations of nonvolatile analog memories. The demonstrated vector-by-vector multiplier, using gate coupling to additional periphery cells, has ~2% precision, limited by the aggregate effect of cell noise, retention, mismatch, process variations, tuning precision, and capacitive crosstalk. A differential version of the multiplier has allowed us to demonstrate sub-3% temperature drift of the output signal in the range between 25 C and 85 C.

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Section: B Array Modification and Cell Tuningmentioning

confidence: 88%

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Guo

Bayat

Prezioso

et al. 2017

2017 IEEE Custom Integrated Circuits Conference (CICC)

Self Cite

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“…For this purpose, NOR memory arrays developed with a 180 nm technology by Silicon Storage Technology, Inc. (SST) [52] are chosen in refs. [53][54][55][56]. The basic memory cell, as depicted in Figure 7a, features a highly asymmetric structure presenting a floating gate only near the source side, with the gate stack at the drain side made only of the tunneling oxide.…”

Section: Memory Transistors As Synaptic Devices In Artificial Neural mentioning

confidence: 99%

Memristive and CMOS Devices for Neuromorphic Computing

et al. 2020

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Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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“…Among different candidates, the resistive switching memories, including phase change and conductive bridge memories, and metaloxide memristors (also known as ReRAM or RRAM [31]) are perhaps the most promising due to their excellent scaling prospects. Their technology, however, is still in need of improvement, which is less of a problem for another excellent candidate, floating gate (FG) memories, e.g., those based on redesigned commercial-grade-embedded NOR flash [22], [32], [33]. Though planar FG cells are less dense than passively integrated memristors, their main advantage is FG cell amplification, which simplifies and reduces the overhead of peripheral circuitry.…”

Section: Introductionmentioning

confidence: 99%

aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator

Bavandpour

Mahmoodi

Strukov

2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

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We introduce ''aCortex,'' an extremely energy-efficient, fast, compact, and versatile neuromorphic processor architecture suitable for the acceleration of a wide range of neural network inference models. The most important feature of our processor is a configurable mixed-signal computing array of vector-by-matrix multiplier (VMM) blocks utilizing embedded nonvolatile memory arrays for storing weight matrices. Analog peripheral circuitry for data conversion and high-voltage programming are shared among a large array of VMM blocks to facilitate compact and energy-efficient analog-domain VMM operation of different types of neural network layers. Other unique features of aCortex include configurable chain of buffers and data buses, simple and efficient instruction set architecture and its corresponding multiagent controller, programmable quantization range, and a customized refresh-free embedded dynamic random access memory. The energy-optimal aCortex with 4-bit analog computing precision was designed in a 55-nm process with embedded NOR flash memory. Its physical performance was evaluated using experimental data from testing individual circuit elements and physical layout of key components for several common benchmarks, namely, Inception-v1 and ResNet-152, two state-of-the-art deep feedforward networks for image classification, and GNTM, Google's deep recurrent network for language translation. The system-level simulation results for these benchmarks show the energy efficiency of 97, 106, and 336 TOp/J, respectively, combined with up to 15 TOp/s computing throughput and 0.27-MB/mm 2 storage efficiency. Such estimated performance results compare favorably with those of previously reported mixed-signal accelerators based on much less mature aggressively scaled resistive switching memories.

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Redesigning commercial floating-gate memory for analog computing applications

Abstract: Abstract-

Cited by 34 publications

References 21 publications

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells

Memristive and CMOS Devices for Neuromorphic Computing

aCortex: An Energy-Efficient Multipurpose Mixed-Signal Inference Accelerator

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