RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip

Silva, Eduardo Alves da; Kreutz, Márcio Eduardo; Zeferino, Cesar Albenes

doi:10.1016/j.sysarc.2019.101633

Cited by 5 publications

(2 citation statements)

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“…This section evaluates the schedulability analysis for direct, indirect, and self-blocking. We implemented the proposed models in C++ and compared their results with the latencies obtained using a cycle-accurate SystemC-based NoC simulator named RedScarf [26]. The number of traffic flows and the size of the buffers varied according to the experiment.…”

Section: Resultsmentioning

confidence: 99%

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

et al. 2023

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Network-on-Chip (NoC) is the ideal interconnection architecture for many-core systems due to its superior scalability and performance. An NoC must deliver critical messages from a realtime application within specific deadlines. A violation of this requirement may compromise the entire system operation. Therefore, a series of experiments considering worst-case scenarios must be conducted to verify if deadlines can be satisfied. However, simulation-based experiments are time-consuming, and one alternative is schedulability analysis. In this context, this work proposes a schedulability analysis to accelerate design space exploration in real-time applications on NoC-based systems. The proposed worstcase analysis estimates the maximum latency of traffic flows assuming direct and indirect blocking. Besides, we consider the size of buffers to reduce the analysis' pessimism. We also present an extension of the analysis, including self-blocking. We conduct a series of experiments to evaluate the proposed analysis using a cycle-accurate simulator. The experimental results show that the proposed solution presents tighter results and runs four orders of magnitude faster than the simulation.INDEX TERMS Network-on-Chip, timing analysis, design space exploration.

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Section: Resultsmentioning

confidence: 99%

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

et al. 2023

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“…Table 1, Table 2, Table 3 present data obtained from experiments carried out using RedScarf [[1], [2]] to evaluate the performance of 64-node on-chip communication architectures submitted to six traffic patterns based on different spatial distributions. The tables present the average latency, the jitter, and the throughput measured by varying the operating frequency.…”

Section: Datamentioning

confidence: 99%

Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment

2019

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This article presents data from an extensive set of simulation-based experiments to compare the performance of on-chip communication architectures. These experiments were performed using the RedScarf simulation environment [1], which is described in the article entitled ‘RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip’ [2]. In the experiments presented here, several intra-chip communication architectures were compared under different traffic patterns. Latency, jitter, and throughput metrics were collected. Data is useful for researchers investigating on-chip communication architectures who need baseline data for comparison.

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Design and implementation of Denial-of-Service attack in network of multiprocessor systems-on-chip with anomaly detection approach

Al-Shoukry

2024

SOCA

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RedScarf: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip

Cited by 5 publications

References 10 publications

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers

Experimental data from the simulation of on-chip communication architectures using RedScarf simulation environment

Design and implementation of Denial-of-Service attack in network of multiprocessor systems-on-chip with anomaly detection approach

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