Reduced-Code Static Linearity Test of Split-Capacitor SAR ADCs Using an Embedded Incremental <inline-formula> <tex-math notation="LaTeX">$\Sigma\Delta$ </tex-math> </inline-formula> Converter

Abstract

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reducedcode technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a lowresolution Incremental Σ∆ converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.