Reduced Complexity Many-Core: Timing Predictability Due to Message-Passing

Mische, Jörg; Frieb, Martin; Stegmeier, Alexander; Ungerer, Theo

doi:10.1007/978-3-319-54999-6_11

Cited by 11 publications

(10 citation statements)

References 16 publications

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“…The lightweight NoC of RC/MC connects the cores. It is called PaterNoster and supports word-size messages, as well as longer messages consisting of multiple shorter messages that are delivered in order [15].…”

Section: Fpga Hardware Costsmentioning

confidence: 99%

PIMP My Many-Core: Pipeline-Integrated Message Passing

Mische

Frieb

Stegmeier

et al. 2020

Int J Parallel Prog

Self Cite

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To improve the scalability, several many-core architectures use message passing instead of shared memory accesses for communication. Unfortunately, Direct Memory Access (DMA) transfers in a shared address space are usually used to emulate message passing, which entails a lot of overhead and thwarts the advantages of message passing. Recently proposed register-level message passing alternatives use special instructions to send the contents of a single register to another core. The reduced communication overhead and architectural simplicity lead to good many-core scalability. After investigating several other approaches in terms of hardware complexity and throughput overhead, we recommend a small instruction set extension to enable register-level message passing at minimal hardware costs and describe its integration into a classical five stage RISC-V pipeline.

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Section: Fpga Hardware Costsmentioning

confidence: 99%

PIMP My Many-Core: Pipeline-Integrated Message Passing

Mische

Frieb

Stegmeier

et al. 2020

Int J Parallel Prog

Self Cite

View full text Add to dashboard Cite

show abstract

“…The Real-Time Capable Many-Core Model proposes many cores with a static switched NoC with TDM-based arbitration [24]. The project also proposes avoiding shared memory altogether and supporting timing analysis by using a fine-grained message passing NoC [25].…”

Section: Network-on-chipmentioning

confidence: 99%

Multicore Models of Communication for Cyber-Physical Systems

Schoeberl

2020

Cyber Physical Systems. Model-Based Design

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Cyber-physical systems are systems where the environment interacts with computers (the cyber part) with real-time constraints. Emerging technologies, such as artificial intelligence and machine learning, call for ever-increasing processing power. However, for real-time systems, we need to prove statically that this processing demand can be performed within strict deadlines. This paper explores a time-predictable multicore architecture for those demanding cyber-physical systems. We explore different models of communication between those multiple cores. We compare the message passing model on top of a network-on-chip with message passing on two forms of shared scratchpad memory.

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“…The NI of PaterNoster is a simple design to support single word packets. The NI is connected to the memory stage of a RISC-V processor [9]. The RISC-V instruction set has been extended with a transmit instruction that blocks until a free slot is available in the NoC and a receive instruction that explores all input buffers in parallel to find a packet for a source address.…”

Section: Related Workmentioning

confidence: 99%

A Minimal Network Interface for a Simple Network-on-Chip

Schoeberl

Pezzarossa

Sparsø

2019

Architecture of Computing Systems – ARCS 2019

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Reduced Complexity Many-Core: Timing Predictability Due to Message-Passing

Cited by 11 publications

References 16 publications

PIMP My Many-Core: Pipeline-Integrated Message Passing

PIMP My Many-Core: Pipeline-Integrated Message Passing

Multicore Models of Communication for Cyber-Physical Systems

A Minimal Network Interface for a Simple Network-on-Chip

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