Reduced electric field in junctionless transistors

Colinge, Jean–Pierre; Lee, Chi‐Woo; Ferain, I.; Akhavan, Nima Dehdashti; Yan, Ran; Razavi, Pedram; Yu, Ran; Nazarov, A. M.; Doria, Rodrigo T.

doi:10.1063/1.3299014

Cited by 299 publications

(127 citation statements)

References 10 publications

Supporting

Mentioning

121

Contrasting

Unclassified

Order By: Relevance

“…7 It has some advantages over surface-channel devices; less degradation of the mobility and near-ideal subthreshold slope. 8,9 In this paper, we report the LF noise behavior in an n-type JLT in which the drain current mainly flows through a bulk channel. An additional conduction was considered in a lightly accumulated channel when the gate voltage is large enough.…”

Section: Low-frequency Noise In Junctionless Multigate Transistorsmentioning

confidence: 99%

Low-frequency noise in junctionless multigate transistors

Jang

Lee

et al. 2011

Applied Physics Letters

Self Cite

View full text Add to dashboard Cite

Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6-30 x 10(16) cm(-3) eV(-1), which is similar to Si-SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers. (C) 2011 American Institute of Physics. (doi:10.1063/1.3569724

show abstract

Section: Low-frequency Noise In Junctionless Multigate Transistorsmentioning

confidence: 99%

Low-frequency noise in junctionless multigate transistors

Jang

Lee

et al. 2011

Applied Physics Letters

Self Cite

View full text Add to dashboard Cite

show abstract

“…The threshold voltage can be further tuned by modifying the printed width of the nanowire. 3,4 The electrical properties of JL transistor have been reported in several publications. [5][6][7][8][9] However, the operation of the device in the diode configuration has not been reported yet.…”

mentioning

confidence: 99%

Characterization of a junctionless diode

Ferain

Akhavan

et al. 2011

Applied Physics Letters

Self Cite

View full text Add to dashboard Cite

A diode has been realised using a silicon junctionless (JL) transistor. The device contains neither PN junction nor Schottky junction. The device is measured at different temperatures. The characteristics of the JL diode are essentially identical to those of a regular PN junction diode. The JL diode has an on/off current ratio of 10(8), an ideality factor of 1.09, and a reverse leakage current of 1 x 10(-14) A at room temperature. The mechanism of the leakage current is discussed using the activation energy (E-A). The turn-on voltage of the device can be tuned by JL transistor threshold voltage. (C) 2011 American Institute of Physics. (doi: 10.1063/1.3608150

show abstract

“…Therefore, the main operation regime for the heavily doped devices (JL) is usually bulk (V TH < V GS < V FB ), due to the large V FB -V TH difference, and for slightly or highly doped devices (AM) is accumulation (V GS > V FB ). Operation in the bulk regime has the advantage of less degradation of carrier mobility due to the perpendicular field (conduction at the middle part of the channel) [10] but suffering from a non-straight forward analytical model in this region [11].…”

Section: Conduction Mechanism In Accumulation-mode and Junctionless Rmentioning

confidence: 99%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

View full text Add to dashboard Cite

a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

show abstract

Reduced electric field in junctionless transistors

Abstract: Access to the full text of the published version may require a subscription. Rights

Cited by 299 publications

References 10 publications

Low-frequency noise in junctionless multigate transistors

Low-frequency noise in junctionless multigate transistors

Characterization of a junctionless diode

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Contact Info

Product

Resources

About