Reduced Electron Temperature in Silicon Multi-Quantum-Dot Single-Electron Tunneling Devices

Abstract

The high-performance room-temperature-operating Si single-electron transistors (SETs) were devised in the form of the multiple quantum-dot (MQD) multiple tunnel junction (MTJ) system. The key device architecture of the Si MQD MTJ system was self-formed along the volumetrically undulated [110] Si nanowire that was fabricated by isotropic wet etching and subsequent oxidation of the e-beam-lithographically patterned [110] Si nanowire. The strong subband modulation in the volumetrically undulated [110] Si nanowire could create both the large quantum level spacings and the high tunnel barriers in the Si MQD MTJ system. Such a device scheme can not only decrease the cotunneling effect, but also reduce the effective electron temperature. These eventually led to the energetic stability for both the Coulomb blockade and the negative differential conductance characteristics at room temperature. The results suggest that the present device scheme (i.e., [110] Si MQD MTJ) holds great promise for the room-temperature demonstration of the high-performance Si SETs.

Room temperature Szilard cycle and entropy exchange at the Landauer limit in a dopant atom double quantum dot silicon transistor

“…This approach extends well-established techniques for the fabrication of dopant atom QD transistors, where dopants are embedded in semiconductor material, for cryogenic temperature operation [50][51][52][53][54]. Our devices also provide a complimentary technique to recent promising methods for few-nanometre/atomic scale QD and SET fabrication capable of liquid nitrogen or RT operation [19,[55][56][57][58][59][60][61]. Examples include Si QDs defined in ultra-thin, ∼5 nm scale Si nanowires [55,56], nanoscale hybrid RT SET/field-effect transistors (FETs) [19], dopant atom QDs in Si nanochannels [57,58], and metal and semiconductor nanocrystal transistors [59][60][61].…”

“…Our DQD transistors are fabricated using a Si/SiO 2 /Si point contact configuration, where P dopant atoms embedded in the ∼10 nm scale SiO 2 tunnel barrier region form QDs. This method may be compared with other recent approaches to the fabrication of few-nanometre/atomic scale QD and SETs, capable of operation at higher temperatures, 77 K up to RT [19,[55][56][57][58][59][60][61]. Examples include Si QDs defined in ultra-thin, ∼5 nm scale Si nanowires [55,56], nanoscale hybrid RT SET/FETs [19], As and P dopant atom QDs in Si point-contacts [57], and metal and semiconductor nanocrystal transistors [59][60][61].…”

“…This method may be compared with other recent approaches to the fabrication of few-nanometre/atomic scale QD and SETs, capable of operation at higher temperatures, 77 K up to RT [19,[55][56][57][58][59][60][61]. Examples include Si QDs defined in ultra-thin, ∼5 nm scale Si nanowires [55,56], nanoscale hybrid RT SET/FETs [19], As and P dopant atom QDs in Si point-contacts [57], and metal and semiconductor nanocrystal transistors [59][60][61]. RT operation of these devices is of great current interest in developing quantum analogues to 'classical' nano FETs, for switching transistor, memory and logic devices [19,56].…”

“…Our devices also provide a complimentary technique to recent promising methods for few-nanometre/atomic scale QD and SET fabrication capable of liquid nitrogen or RT operation [19,[55][56][57][58][59][60][61]. Examples include Si QDs defined in ultra-thin, ∼5 nm scale Si nanowires [55,56], nanoscale hybrid RT SET/field-effect transistors (FETs) [19], dopant atom QDs in Si nanochannels [57,58], and metal and semiconductor nanocrystal transistors [59][60][61]. These devices are of great current interest in providing quantum device alternatives to 'classical' Si nan-oFETs, where minimum feature size is already at the <10 nm scale [62].…”

“…These devices are of great current interest in providing quantum device alternatives to 'classical' Si nan-oFETs, where minimum feature size is already at the <10 nm scale [62]. RT QDs and SETs have now been reported for applications as switching transistors [19,55], multivalue [56] and probabilistic logic devices [19], memory cells [19], and meterological current standards [63,64].…”