Reduced n⁺/p⁺-spacing with high latchup hardness in self-aligned double well CMOS technology

Single Event Latch-Up Hardening Using TCAD Simulations in 130 nm and 65 nm Embedded SRAM in Flash-Based FPGAs

“…Since it may not be possible for IC designers to make changes in the process, design and layout techniques must be used for reducing the resistances along the paths. This can be accomplished through the use of multiple contacts to and that are physically closer to the sensitive area [5], [8], [9], [10]. The number of contacts and their spacing should be determined such that the largest expected transient current cannot produce enough potential drop to forward bias the emitter-base junctions, and thus the latch-up process can't be initiated.…”

“…11. Increasing the to spacing is one of the mitigation techniques to reduce SEL sensitivity [8]. As the spacing increases the decreases, and the " -product" decreases significantly for the case of dual-well CMOS technology [16].…”

“…Typical design practices employed to reduce latch-up susceptibility include (1) increasing the to spacing [8], (2) adding guard-bands in the well to reduce the gain of the parasitic transistors and control the potential of Manuscript received November 14, 2014; revised January 28, 2015; accepted June 18, 2015.…”