Reduced overhead soft error mitigation using error control coding techniques

Prasanth, V.; Singh, Virendra; Parekhji, Rubin

doi:10.1109/iolts.2011.5993831

Cited by 6 publications

(1 citation statement)

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“…This can significantly vary the results of the estimated SER and the rate of multiple bit-flips. In [31], it is assumed that, a gate can possibly affect multiple outputs in its fanout cone, but this assumption is neither verified nor quantified. In [32], a transient fault simulator based on pulse and delay models is built.…”

Section: Related Workmentioning

confidence: 99%

On the likelihood of multiple bit upsets in logic circuits

Rao,

Sarik,

Desai

2014

Preprint

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Soft errors have a significant impact on the circuit reliability at nanoscale technologies. At the architectural level, soft errors are commonly modeled by a probabilistic bit-flip model. In developing such abstract fault models, an important issue to consider is the likelihood of multiple bit errors caused by particle strikes. This likelihood has been studied to a great extent in memories, but has not been understood to the same extent in logic circuits. In this paper, we attempt to quantify the likelihood that a single transient event can cause multiple bit errors in logic circuits consisting of combinational gates and flip-flops. In particular, we calculate the conditional probability of multiple bit-flips given that a single bit flips as a result of the transient. To calculate this conditional probability, we use a Monte Carlo technique in which samples are generated using detailed post-layout circuit simulations. Our experiments on the ISCAS'85 benchmarks and a few other circuits indicate that, this conditional probability is quite significant and can be as high as 0.31. Thus we conclude that multiple bit-flips must necessarily be considered in order to obtain a realistic architectural fault model for soft errors.

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Section: Related Workmentioning

confidence: 99%