Reducing bit width of extrinsic memory inturbo decoder realisations

Vogt, Juliane; Ertel, J.; Finger, Adolf

doi:10.1049/el:20001177

Cited by 14 publications

(23 citation statements)

References 1 publication

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“…This provides an extremely simple and fast encoding and decoding circuit, further shrinks the extrinsic memory. Similar work for max-log-MAP was recently published in [14].…”

Section: Figuresupporting

confidence: 58%

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Energy efficient turbo decoding for 3G mobile

Garrett¹,

Xu²,

Nicol³

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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The requirement of turbo decoding in 3G wireless standards has forced handset designers to consider power consumption issues in their implementations. The phenomenal performance of turbo codes comes at the expense of computation. Primarily this paper looks at methods of substantially reducing the power consumption for the decoding operation, making it feasible to integrate turbo decoders into a low power handset. The techniques presented include early termination of the turbo process, encoding of extrinsic information to reduce the memory size, and disabling portions of the MAP algorithm when the results will not affect the decoded output. The net result of these techniques is almost a 70% reduction in power over a fixed 6 iteration, 8-state baseline turbo decoder at 2 dB of signal to noise ratio (SNR).

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“…This provides an extremely simple and fast encoding and decoding circuit, further shrinks the extrinsic memory. Similar work for max-log-MAP was recently published in [14].…”

Section: Figuresupporting

confidence: 58%

“…The companding function has additional benefits not identified in [14] in that in some cases, the encoding provides better performance than the regular extrinsic system. Figure 5 demonstrates a complete system simulation of a turbo system with and without the companded extrinsics (block size of 840, 6 iterations, and 8-bit input symbols).…”

Section: Figurementioning

confidence: 99%

Energy efficient turbo decoding for 3G mobile

Garrett¹,

Xu²,

Nicol³

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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“…The BER performances are measured for a coding rate of 1/2. Although some approximations are applied in deriving the proposed conversions, they lead to only a slight degradation of the signal-to-noise ratio, about less than 0.1 dB, since the extrinsic information does not need to be exact in decoding [4]. Consequently, we can reduce the number of extrinsic information values to be exchanged without inducing a considerable loss of error-correcting capability.…”

Section: Resultsmentioning

confidence: 99%

“…Although nonuniform quantization adopted in single-binary turbo decoding can be applied to reduce the extrinsic memory size [4], the large memory size incurred by the increased number of extrinsic information values is still a major obstacle in implementing a nonbinary turbo decoder [5].…”

Section: Introductionmentioning

confidence: 99%

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

Kim

Park

2009

IEEE Trans. Circuits Syst. II

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Abstract-Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input-softoutput (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in doublebinary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%.Index Terms-Double-binary turbo codes, extrinsic information, maximum a posteriori algorithm, turbo decoding.

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“…A very large part of the overall power consumption is therefore imputable to the memory accesses of the extrinsic information and the path metrics. In [11], a nonlinear quantization approach was proposed to reduce the bit width of the extrinsic information to 3 bits by adding a transformation module and an inverse transformation module into the decoder.…”

Section: Power Reduction Techniquementioning

confidence: 99%

High-Speed and Low-Power Design of Parallel Turbo Decoder

Roy

Fortier

2005 IEEE International Symposium on Circuits and Systems

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This paper presents the high speed and low power design of a turbo decoder with parallel architecture. To solve the memory conflict problem of extrinsic information in such parallel architectures, a two-level mapping approach is proposed for designing a collision-free parallel interleaver. Since the warm-up process in the parallel architecture increases the decoding delay, a new parallel architecture without warm-up is proposed for high speed applications. The proposed parallel architecture increases decoding speed by 6-50% for a 16-parallel decoder. To reduce the power consumption of the decoder with parallel architecture, a simple truncation approach is proposed to reduce the storage requirement of the extrinsic information and path metrics without any extra hardware cost. The proposed truncation approach reduces the power consumption with little performance degradation. 0-7803-8834-8/05/$20.00 ©2005 IEEE.

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Reducing bit width of extrinsic memory inturbo decoder realisations

Cited by 14 publications

References 1 publication

Energy efficient turbo decoding for 3G mobile

Energy efficient turbo decoding for 3G mobile

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

High-Speed and Low-Power Design of Parallel Turbo Decoder

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