Reducing branch misprediction penalties via dynamic control independence detection

Abstract

This paper presents the concept of dynamic control independence (DCl) and shows how it can be detected and exploited in an out-of-order superscalar processor to reduce the performance penalties of branch mispredictions. We show how DCI can be leveraged during branch misprediction recovery to reduce the number of instructions squashed on a misprediction as well as how it can be used to avoid predicting unpredictable branches by fetching instructions out-of-order A realistic implementation is described and evaluated using six SPECint95 benchmarks. We show that exploiting DCI during branch misprediction recovety improves pe$ormance by 0.9-9.9% on a I-wide processol; by I&11.2% on an b-wide processor and by 1.9-15.3% on a 12-wideprocessol: We also show that using DCI information to fetch instructions out-of-order when an unpredictable branch is encountered potentially improves performance by 0.9-15.2% on a I-wide processol: by 2.0-14.8% on an 8-wide processor and by 2.6-16.2% on a 12-wide processor: Some of the largest performance gains are observed on go and gee, which have traditionally posed the most d@cult challenge to aggressive branch prediction techniques.

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

“…Figure 6 shows the performance improvement of dynamichammock-predication, dual-path, multipath, and DMP over the baseline processor. The average IPC improvement over all benchmarks is 3.5% for dynamic-hammock-predication, 4.8% for dual-path, 8.8% for multipath, 11 and 19.3% for DMP. DMP improves the IPC by more than 20% on vpr (58%), mcf (47%), parser (26%), twolf (31%), compress (23%), and ijpeg (25%).…”

“…Several hardware mechanisms were proposed to exploit control flow independence [35,36,11,8,16]. These techniques aim to avoid flushing the processor pipeline if the processor is known to be at a control-independent point in the program when a mispredicted branch is resolved.…”

Control Flow Optimization Via Dynamic Reconvergence Prediction

“…Finally, techniques have been proposed to salvage some of the work performed on the incorrect control path via squash reuse [17], Control Independence [11,12,6], and Register Integration [13].…”

“…However, target prediction for indirect jumps is typically less accurate than conditional branch prediction, and may contribute a significant fraction of total control misspeculations. This heightens the importance of identifying reconvergence points for these instructions if it provides additional opportunity for techniques which mitigate misprediction costs [11,12,6,5].…”

Chip multi-processor scalability for single-threaded applications

“…While such selective replay recovery mechanisms have been proposed [6], [10], most aggressive processors simply squash all instructions following a misspeculated branch due to the complexity of identifying control re-convergence and re-inserting instructions into the middle of the scheduling window.…”