Reducing capacity and conflict misses using Set Saturation Levels

Rolan, Dyer; Fraguela, Basilio B.; Doallo, Ramón

doi:10.1109/hipc.2010.5713184

Cited by 5 publications

(3 citation statements)

References 15 publications

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“…From left to right, a non‐thread aware DIP , which selects between BIP or LRU insertion depending on which one is working better in the cache, provides less performance than a non‐thread aware SBC. The BSBC , which combines BIP and SBC in private caches, but which, unlike TAMR2, is unaware of the existence, and the behavior of the different applications performs much better by coordinating efficiently placement and insertion policies to reduce mapping and replacement misses. TADIP thread‐awareness applied to insertion policy management brings large advantages in shared caches, as seen in .…”

Section: Thread‐aware Mapping and Replacement Miss Reduction Results mentioning

confidence: 99%

“…The traditional problems due to the load unbalance among cache sets and the suboptimal replacement algorithms present in single core environments, which the SSL metric has been successfully proved to detect , are found in shared caches as well. In fact, new misses of both kinds appear in shared caches due to the effects of the joint working set of the applications sharing them.…”

Section: Discussionmentioning

confidence: 99%

“…The RRIP policies in TADRRIP, TAMR2–RRIP, and SHiP use two bits to characterize the re‐reference prediction and hit priority update policy . Finally, we also evaluate the Bimodal Set Balancing Cache (BSBC) , which proposes the combination of BIP and SBC in private caches, and is thus unaware of the existence and the behavior of the different applications. TAMR2 and BSBC use a destination set selector (DSS) of four entries like the one in .…”

Section: Simulation Environmentmentioning

confidence: 99%

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A fine‐grained thread‐aware management policy for shared caches

Rolan¹,

Andrade

Fraguela

et al. 2013

Concurrency and Computation

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SUMMARYTwo of the main sources of inefficiency in current caches are the non‐uniform distribution of the memory accesses across the cache sets, which causes misses due to the mapping restrictions of non fully associative caches and the access patterns with little locality that degrade the performance of caches under the traditional least recently used. replacement policy. This paper proposes a technique to tackle in a coordinated way both kinds of problems in the context of chip multiprocessors, whose last level caches can be shared by threads with different patterns of locality. Our proposal, called thread‐aware mapping and replacement miss reduction (TAMR2) policy, tracks the behavior of each thread in each set in order to decide the appropriate combination of policies to deal with these problems. Despite its small overhead, TAMR2 achieved in our experiments average power consumption and memory latency reductions of 10% and 12%, respectively, resulting in an average throughput improvement of 5.6%, relative to a traditional cache design using four cores. TAMR2 also outperformed many recent related approaches in the field. Copyright © 2013 John Wiley & Sons, Ltd.

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Section: Thread‐aware Mapping and Replacement Miss Reduction Results mentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%