Reducing complexity in tree-like computer interconnection networks

Optical Switching and Networking

2011

Self Cite

Interconnection networks arranged as k-ary n-trees or spines are widely used to build highperformance computing clusters. Current blade-based technology allows the integration of the first level of the network together with the compute elements. The remaining network stages require dedicated rack space. In most systems one or several racks house the upper network stages, separated from the compute elements. This incurs significant additional costs, especially if a rack containing only a few switches has to be added.In this paper we propose and evaluate the performance and power-consumption of an alternative arrangement that connects elements in a cube-like topology. Building an indirect cube topology requires only the use of the switches that are integrated within the compute elements and also simplifies deployment. We explore a wide variety of system scales, ranging from 120 to 7680 compute nodes, in order to find out to which size the proposed topology can scale while keeping adequate performance levels and low power demands. An additional advantage of our proposal is that the same equipment can be reused to form a tree-based topology if a performance boost is needed.

Section: Experimental Set-upsupporting

confidence: 63%

“…Previous studies in cost-effective topologies for large-scale clusters have analyzed thinned tree topologies [21]. As future work, we plan to compare these thin trees against indirect cubes in order to explore if there is any limit of the slimming factor for which the indirect cube outperforms the trees.…”

Section: Discussionmentioning

confidence: 99%

Indirect cube: A power-efficient topology for compute clusters

Optical Switching and Networking

2011

Self Cite

“…A detailed model of the SpiNNaker IN was implemented in INSEE [23], a time-driven simulator that has been previously used in several high performance computing environment studies [4,16,17]. Note that SpiNNaker has a completely asynchronous design, so the use of a time-driven approach introduces a very fine-grain time discretization, with little influence on the results.…”

Section: Experimental Work 41 Model Of the Systemmentioning

confidence: 99%

Understanding the interconnection network of SpiNNaker

Luján

Proceedings of the 23rd International Conference on Supercomputing

et al. 2009

Self Cite

SpiNNaker is a massively parallel architecture designed to model large-scale spiking neural networks in (biological) real-time. Its design is based around ad-hoc multi-core System-on-Chips which are interconnected using a two-dimensional toroidal triangular mesh. Neurons are modeled in software and their spikes generate packets that propagate through the on-and inter-chip communication fabric relying on custom-made on-chip multicast routers. This paper models and evaluates large-scale instances of its novel interconnect (more than 65 thousand nodes, or over one million computing cores), focusing on real-time features and fault-tolerance. The key contribution can be summarized as understanding the properties of the feasible topologies and establishing the stable operation of the SpiNNaker under different levels of degradation. First we derive analytically the topological characteristics of the network, which are later confirmed by experimental work. With the computational model developed, we investigate the topology of SpiNNaker, and compare it with a standard 3-dimensional torus. The novel emergency routing mechanism, implemented within the routers, allows the topology of SpiNNaker to be more robust than the 3-dimensional torus, regardless of the latter having better topological characteristics. Furthermore, we obtain optimal values of two router parameters related with livelock and deadlock avoidance mechanisms.

“…Figures of merit usually did not show how placement strategies affect the runtime of an application instance, but just the completion time of a list of jobs. In [16] we paid attention to tree-based topologies and relied on contiguous allocation of tasks to, by means of an efficient exploitation of communication locality, dilute or even invert the potentially negative effects of reducing the bisection bandwidth of the network. Interestingly, in [10] authors showed how the requirement of contiguous allocation may cause poor utilization of the system due to external or internal fragmentation.…”

Section: Related Workmentioning

confidence: 99%

Effects of Job and Task Placement on Parallel Scientific Applications Performance

Pascual

2009 17th Euromicro International Conference on Parallel, Distributed and Network-Based Processing

2009

Self Cite

Abstract-this paper studies the influence that task placement may have on the performance of applications, mainly due to the relationship between communication locality and overhead. This impact is studied for torus and fat-tree topologies. A simulation-based performance study is carried out, using traces of applications and application kernels, to measure the time taken to complete one or several concurrent instances of a given workload. As the purpose of the paper is not to offer a miraculous task placement strategy, but to measure the impact that placement have on performance, we selected simple strategies, including random placement. The quantitative results of these experiments show that different workloads present different degrees of responsiveness to placement. Furthermore, both the number of concurrent parallel jobs sharing a machine and the size of its network has a clear impact on the time to complete a given workload. We conclude that the efficient exploitation of a parallel computer requires the utilization of scheduling policies aware of application behavior and network topology.