Reducing dynamic and leakage energy in VLIW architectures

Abstract

The mobile computing device market has been growing rapidly. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in the future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule slacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present three compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. Integer ALU (IALU) components operating with multiple supply voltages are designed to provide different lowenergy versions that possess different operational latencies. The goal of the first technique explored is to maximize the number of operations mapped to IALU components with the lowest energy consumption without extending the schedule length. We also consider a variant of this technique that saves more energy at the cost of some performance loss. The second technique uses two leakagecontrol mechanisms to reduce leakage energy consumption when no operations are scheduled in the component. Our evaluation of these two approaches, using fifteen benchmarks, shows that based on the number and duration of slacks, the availability of low-energy functional units and the relative magnitude of leakage and dynamic energy, either leakage or dynamic energy consumption, will provide more energy gains. Finally, we provide a unified energy-optimization strategy that integrates both dynamic and leakage energy-reduction schemes. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit-level simulation. Our results show that the unified scheme generates better results than using either of dynamic and leakage energy-reduction techniques independently.

Design space exploration for an embedded processor with flexible datapath interconnect

“…In contrast to the works cited, FlexTools addresses application efficiency, while at the same time being capable of leveraging energy benefits offered by ASICs. Zhang et al [18] independently combine the techniques similar to the ones in [16] with traditional circuit-based techniques, like power gating, to achieve energy efficiency. FlexTools provides an integrated toolchain that helps achieve optimal results at design time.…”

Leakage-Aware Modulo Scheduling for Embedded VLIW Processors

“…In this paper, we use the energy model in [8] to calculate the leakage energy and total energy. Energy-efficient system-level scheduling techniques with considerations of leakage power dissipation have been explored in [12][13][14][15][16][17][18][19][20][21]. Luo and Jha [15] addressed the problem of variable-voltage scheduling of multirate periodic task graphs in heterogeneous distributed real-time embedded systems.…”