Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures

Sundaram, S.L.; Carlson, A.C.

doi:10.1109/icmts.1990.67903

Cited by 11 publications

(1 citation statement)

References 2 publications

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“…It is well-known that many device and SPICE parameters are correlated [2], [3], [6]. Often these correlations stem from a common underlying process step.…”

Section: A Feature Extraction: Determining the Number Of Underlying mentioning

confidence: 99%

Analysis of mixed-signal manufacturability with statistical technology CAD (TCAD)

Hanson

Goossens

Redford³

et al. 1996

IEEE Trans. Semicond. Manufact.

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Abstruct-We have developed a methodology which combines technology CAD (TCAD) simulation with statistical analysis of empirical data to predict and control the manufacturability of IC fabrication processes. As a result, manufacturing tolerance or sigma-based models (also known as worst-case models) can be determined before a significant sample size of fabricated devices can be characterized. Early on in the development cycle, empirical data is collected, and models built from simulated dataL are refined. These revised models are used to determine process control limits, and optimize in-line and electrical test measurement (E-test) for maximum observability of variation. As the process is stabilized, further refined models are used to perform yield diagnosis and tolerance analysis of circuits. This methodology has been applied to a number of BJT and submicrometer CMOS processes to create predictive sigma-based models, modify the fabrication recipe to meet objective specifications as development proceeds, and finally use them to control the manufacturing line.

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“…It is well-known that many device and SPICE parameters are correlated [2], [3], [6]. Often these correlations stem from a common underlying process step.…”

Section: A Feature Extraction: Determining the Number Of Underlying mentioning

confidence: 99%