Reducing fetch architecture complexity using procedure inlining

Santana, Oliverio J.; Ramírez, Alex; Valero, Mateo

doi:10.1109/intera.2004.1299514

“…In [14], Santana et al propose software techniques to reorganize the code so that the fetch engine complexity can be reduced. In a similar way, Ramirez et al [15] also propose compiler optimizations to improve the layout of instructions.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware fetch mechanism: trace cache and BTB customization

Chaver¹,

Rojas²,

Pinuel³

et al. 2005

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.

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1A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on program behavior, can be either insufficient or an overkill. We introduce a phase-based adaptive fetch mechanism that can be dynamically adjusted based on feedback information of the program behavior. This design adds very little hardware complexity and relegates complex tasks to the software components. It is also very effective: saving 26.8% and 34.1% fetch energy on average compared with a conventional and a trace cache-based fetch unit, respectively. At the same time, performance is improved by 5.7% and 0.6%, respectively.

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“…In [14], Santana et al propose software techniques to reorganize the code so that the fetch engine complexity can be reduced. In a similar way, Ramirez et al [15] also propose compiler optimizations to improve the layout of instructions.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware fetch mechanism

Chaver

¹

,

Rojas

²

,

Piñuel

³

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

6

0

View full text Add to dashboard Cite

1A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on program behavior, can be either insufficient or an overkill. We introduce a phase-based adaptive fetch mechanism that can be dynamically adjusted based on feedback information of the program behavior. This design adds very little hardware complexity and relegates complex tasks to the software components. It is also very effective: saving 26.8% and 34.1% fetch energy on average compared with a conventional and a trace cache-based fetch unit, respectively. At the same time, performance is improved by 5.7% and 0.6%, respectively.

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“…For removing backward conditional branches, we present a loop-stream predictor, that is, a version of the stream predictor that is able to predict high-level loop structures, making it possible to combine all of the iterations of simple loops into a single long virtual stream. Finally, in order to remove function calls and returns, we apply aggressive procedure inlining [7] to replace procedure calls by the called procedures.…”

Section: Introductionmentioning

confidence: 99%

Enlarging Instruction Streams

Desmet

¹

,

Verbaeten

²

,

Joosen

³

et al. 2007

IEEE Trans. Comput.

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Abstract-The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks, a stream. The long length of instruction streams makes it possible for the stream fetch engine to provide a high fetch bandwidth and to hide the branch predictor access latency, leading to performance results close to a trace cache at a lower implementation cost and complexity. Therefore, enlarging instruction streams is an excellent way to improve the stream fetch engine. In this paper, we present several hardware and software mechanisms focused on enlarging those streams that finalize at particular branch types. However, our results point out that focusing on particular branch types is not a good strategy due to Amdahl's law. Consequently, we propose the multiple-stream predictor, a novel mechanism that deals with all branch types by combining single streams into long virtual streams. This proposal tolerates the prediction table access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding. Moreover, it provides high-performance results which are comparable to state-of-the-art fetch architectures but with a simpler design that consumes less energy.

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Reducing fetch architecture complexity using procedure inlining

Abstract: Abstract

Cited by 4 publications

References 29 publications

Energy-aware fetch mechanism: trace cache and BTB customization

Energy-aware fetch mechanism: trace cache and BTB customization

Energy-aware fetch mechanism

Enlarging Instruction Streams

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