Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns

Szafarczyk, Robert; Nabi, Syed Waqar; Vanderbauwhede, Wim

doi:10.1109/fpl57034.2022.00033

Cited by 1 publication

(2 citation statements)

References 17 publications

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“…Szafarczyk et al extended modulo-scheduled HLS tools with support for selective dynamic scheduling by breaking up the DDG of an input code into multiple modulo-scheduling instances based on compiler analysis that determines where dynamic scheduling is beneficial [19]. The separate modulo scheduling instances communicate via latency-insensitive channels -a construct available in most static HLS tools.…”

Section: B Combining Static and Dynamic Schedulingmentioning

confidence: 99%

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A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

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Dynamically scheduled high-level synthesis (HLS) achieves a higher throughput on codes with unpredictable memory accesses compared to statically scheduled HLS. However, the increased throughput comes at the price of increased resource usage and critical path length, resulting in lower clock frequency. The decrease in clock frequency can be significant, often nullifying any throughput improvements over static scheduling. Recent work presented methods for combining static and dynamic scheduling to achieve high throughput circuits with a fast critical path for dynamic codes. However, circuits that require dynamically scheduled memory still suffer from a decreased frequency. This paper fills this gap by presenting a method for achieving dynamically scheduled memory operations in HLS with a high frequency. Dynamic scheduling of memory operations is realized with a load-store queue (LSQ). We present a novel LSQ design adapted to the nature of spatial architectures with aggressive specialization to the target code -a unique opportunity in HLS. Our LSQ design works for both on-chip and off-chip memory and is integrated with a compiler that combines dynamic and static scheduling. We show a method to speculatively allocate addresses to our LSQ, significantly increasing pipeline parallelism in codes that could not benefit from an LSQ before. In stark contrast to traditional load value speculation, our approach adds no overhead on misspeculation. On a set of ten benchmarks, we show that our approach can achieve an up to 10× speedup on average against static HLS, and an up to 4× speedup against dynamic HLS that uses an LSQ from previous work, while also using several times fewer resources and scaling to larger queues.

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Section: B Combining Static and Dynamic Schedulingmentioning

confidence: 99%

“…al. to enable dynamically scheduled loads in static HLS [19], using existing compiler analysis to determine which base memory addresses require an LSQ [29]. Each selected base address will use its own LSQ.…”

Section: A Dynamically Scheduled Memory In Static Hlsmentioning

confidence: 99%

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

View full text Add to dashboard Cite

show abstract

Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns

Abstract: There may be differences between this version and the published version. You are advised to consult the published version if you wish to cite from it.

Cited by 1 publication

References 17 publications

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

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