Reducing latency overhead caused by using LDPC codes in NAND flash memory

Zhao, Wenzhe; Dong, Guiqiang; Sun, Hongbin; Zheng, Nanning; Zhang, Tong

doi:10.1186/1687-6180-2012-203

Cited by 16 publications

(10 citation statements)

References 28 publications

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“…For example, starting with a graph empty of edges E = ∅ and continuing with the loop do (Procedure Insert Circulant) until (a predefined regular or quasi-regular distribution is obtained), a PEG-like construction can be made leading directly to a QC-LDPC code of any submatrix size, binary or nonbinary. A promising application is a binary codes optimization for hard decision decoding, for example used in a NAND flash memory controllers, which are known to demand codes with relatively large column weights [11], possibly with quasi-regular distribution.…”

Section: Procedures Nb-ldpc Quasi-regular Code Construction With a Lowmentioning

confidence: 99%

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

Sulek

2016

IEEE Commun. Lett.

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Nonbinary ultra sparse codes, particularly regular cycle codes, are known to approach Shannon-limit performance as the Galois field GF(q) order is sufficiently large. Good cycle codes can result from a class of algebraically defined graphs called cages. Meanwhile, when smaller q is desirable, the cycle codes are outperformed by quasi-regular codes. In this letter, we propose a code construction method that takes a cage as a starting point and then progressively inserts a few additional edges into the graph. The edge insertion is terminated as soon as the code performance stops improving. Our simulation results show that the obtained quasi-regular codes outperform cyclic codes for fields up to GF(64) and its performance is slightly better than the quasi-regular improved-Progressive Edge Growth-based codes. The proposed algorithm preserves the block-circulant structure of the initial cage-based graph; therefore, it can be used for structured or quasi-cyclic codes design.

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Section: Procedures Nb-ldpc Quasi-regular Code Construction With a Lowmentioning

confidence: 99%

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

Sulek

2016

IEEE Commun. Lett.

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“…Dong et al [4] propose a non-uniform sensing strategy that can increase the information contained in LLRs. Zhao et al [19,18] propose a progressive sensing and decoding strategy that incrementally increases the precision of LLRs in a fail-and-retry manner. Dong et al [5] further propose compressing the sensing results to reduce memory-tocontroller data transferring latency.…”

Section: Background and Related Workmentioning

confidence: 99%

“…LDPC offers stronger error-correcting capability than conventional ECCs such as Bose-ChaudhuriHocquenghem (BCH) codes. However, LDPC's complex decoding algorithm imposes performance overhead on SSDs [5,18,19].…”

Section: Introductionmentioning

confidence: 99%

EC-Cache

Liu

Chuang

Yang

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the "error locality" of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.

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“…Flash memory adopts a charge stored in a silicon nitride as the trapping layer, which exhibits significantly reduced defect-related leakage current and very low SILC as compared to SiO 2 with a similar EOT [ 64 ]. Such a relentless reduction of device dimensions has many challenges like retention, endurance, reduction in the number of electrons in the FG, dielectric leakage, cell-to-cell cross talk, threshold voltage shift, and reduction in memory window margins [ 65 , 66 ]. The key concept of real scaling issues such as material and structural changes in Flash memory technologies is provided in detail in the next distinct part.…”

Section: Reviewmentioning

confidence: 99%

Overview of emerging nonvolatile memory technologies

et al. 2014

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Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

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Reducing latency overhead caused by using LDPC codes in NAND flash memory

Cited by 16 publications

References 28 publications

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

Nonbinary Quasi-Regular QC-LDPC Codes Derived From Cycle Codes

EC-Cache

Overview of emerging nonvolatile memory technologies

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