Reducing Packet Dropping in a Bufferless NoC

Gómez, C.; Gómez, María E.; López, Pedro; Duato, J.

doi:10.1007/978-3-540-85451-7_97

Cited by 34 publications

(32 citation statements)

References 8 publications

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“…In these networks, the topology is often the most influential factor on performance [16]. Alternatively, flits or packets under contention can be dropped and re-submitted by their source [8].…”

Section: Related Workmentioning

confidence: 99%

Router designs for elastic buffer on-chip networks

Dally

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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This paper explores the design space of elastic buffer (EB) routers by evaluating three representative designs. We propose an enhanced two-stage EB router which maximizes throughput by achieving a 42% reduction in cycle time and 20% reduction in occupied area by using look-ahead routing and replacing the three-slot output EBs in the baseline router of [17] with two-slot EBs. We also propose a singlestage router which merges the two pipeline stages to avoid pipelining overhead. This design reduces zero-load latency by 24% compared to the enhanced two-stage router if both are operated at the same clock frequency; moreover, the single-stage router reduces the required energy per transferred bit and occupied area by 29% and 30% respectively, compared to the enhanced two-stage router. However, the cycle time of the enhanced two-stage router is 26% smaller than that of the single-stage router.

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Section: Related Workmentioning

confidence: 99%

Router designs for elastic buffer on-chip networks

Dally

2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

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“…Bufferless 1 NoC design has recently been evaluated as an alternative to traditional virtual-channel buffered routers [38,19,16,31,52]. It is appealing mainly for two reasons: reduced hardware cost, and simplicity in design.…”

Section: Why Bufferless? (And When?)mentioning

confidence: 99%

“…However, this age-based priority mechanism is expensive [36,19] both in header information and in arbitration critical path. Alternatively, some bufferless routing proposals do not provide or explicitly show deterministic livelock-freedom guarantees [19,16,52]. This can lead to faster arbitration if it allows for simpler priority schemes.…”

Section: Livelock Freedommentioning

confidence: 99%

“…However, several networks eliminate buffers without deflection. BPS [16] proposes bufferless routing that drops packets under contention. SCARAB [19] builds on BPS by adding a dedicated circuit-switched NACK network to trigger retransmits.…”

Section: Related Workmentioning

confidence: 99%

“…In particular, one line of recent work has investigated how to eliminate in-router buffers altogether [38,19,16], or minimize them with alternative designs [25,26,39]. The completely bufferless designs either drop [19,16] or misroute (deflect) [38] flits when contention occurs. Eliminating buffers is desirable: buffers draw a significant fraction of NoC power [21] and area [17], and can increase router latency.…”

Section: Introductionmentioning

confidence: 99%

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CHIPPER: A low-complexity bufferless deflection router

Fallin

Craik

Mutlu

2011

2011 IEEE 17th International Symposium on High Performance Computer Architecture

165

222

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As Chip Multiprocessors (CMPs) scale to tens or hundreds of nodes, the interconnect becomes a significant factor in cost, energy consumption and performance. Recent work has explored many design tradeoffs for networks-on-chip (NoCs) with novel router architectures to reduce hardware cost. In particular, recent work proposes bufferless deflection routing to eliminate router buffers. The high cost of buffers makes this choice potentially appealing, especially for lowto-medium network loads.However, current bufferless designs usually add complexity to control logic. Deflection routing introduces a sequential dependence in port allocation, yielding a slow critical path. Explicit mechanisms are required for livelock freedom due to the non-minimal nature of deflection. Finally, deflection routing can fragment packets, and the reassembly buffers require large worst-case sizing to avoid deadlock, due to the lack of network backpressure. The complexity that arises out of these three problems has discouraged practical adoption of bufferless routing.To counter this, we propose CHIPPER (Cheap-Interconnect Partially Permuting Router), a simplified router microarchitecture that eliminates in-router buffers and the crossbar. We introduce three key insights: first, that deflection routing port allocation maps naturally to a permutation network within the router; second, that livelock freedom requires only an implicit token-passing scheme, eliminating expensive age-based priorities; and finally, that flow control can provide correctness in the absence of network backpressure, avoiding deadlock and allowing cache miss buffers (MSHRs) to be used as reassembly buffers. Using multiprogrammed SPEC CPU2006, server, and desktop application workloads and SPLASH-2 multithreaded workloads, we achieve an average 54.9% network power reduction for 13.6% average performance degradation (multiprogrammed) and 73.4% power reduction for 1.9% slowdown (multithreaded), with minimal degradation and large power savings at low-to-medium load. Finally, we show 36.2% router area reduction relative to buffered routing, with comparable timing.

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