Reducing Power Consumption of GPGPUs Through Instruction Reordering

Aghilinasab, Homa; Sadrosadati, Mohammad; Samavatian, Mohammad Hossein; Sarbazi-Azad, Hamid

doi:10.1145/2934583.2934606

Cited by 9 publications

(10 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One of the main GPU resources that is frequently underutilized is the execution units. Idle execution units consume significant static power, which increases the total GPU power consumption [2,3,46,105]. Reducing the static power of the GPU execution units is a major challenge for two reasons.…”

Section: Introductionmentioning

confidence: 99%

“…As an example, previous work finds that the execution units of NVIDIA GTX 480 GPUs [74,78] are the most power-consuming components of the architecture, contributing to 20% of the total GPU power [60]. Second, about 50% of the power consumption in the execution units is due to the static power [2,3,60,105].…”

Section: Introductionmentioning

confidence: 99%

“…To alleviate the static power overheads of partial-and full-lane idleness, previous proposals employ Power-Gating (PG), which cuts off power to the idle execution units [1][2][3]105]. PG techniques intrinsically impose power and performance overheads, making them beneficial only when the idle periods are large enough (larger than the cost/benefit break-even point of PG; see Section 2.2).…”

Section: Introductionmentioning

confidence: 99%

“…PG techniques intrinsically impose power and performance overheads, making them beneficial only when the idle periods are large enough (larger than the cost/benefit break-even point of PG; see Section 2.2). Previous studies [2,3,105] show that the idle time of GPU execution units is fragmented into short but frequent periods, seriously limiting the potential of PG. Blindly applying PG introduces more overhead than improvement and defeats the purpose of power efficiency [2,105].…”

Section: Introductionmentioning

confidence: 99%

“…Blindly applying PG introduces more overhead than improvement and defeats the purpose of power efficiency [2,105]. Accordingly, previous proposals attempted to improve the opportunity of PG by defragmenting idle periods of the execution units [2,3,105]. For example, pattern-aware scheduling [105] proposes a warp scheduler to enlarge the length of the idle periods, which result from partial-lane idleness, to increase the opportunity of PG.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

Self Cite

View full text Add to dashboard Cite

Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP, a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period M. Sadrosadati performed part of this work at ETH Zürich. L. Orosa was supported by FAPESP fellowship 2016/18929-4.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations