Reducing power density through activity migration

Heo, Su-Jeong; Barr, Kenneth C.; Asanović, Krste

doi:10.1145/871506.871561

Cited by 241 publications

(193 citation statements)

References 6 publications

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“…Due to 3D stack structure, the heat generated by the heat sources must flow through the body of the 3D tiers, and end at the environment interface (ambient) where it is spread through natural convection. Then, the heat flow inside this structure is diffusive in nature and hence, is modeled by its equivalence to an electronic RC circuit [8][9][10]. This is done by first dividing the entire structure into small cubical thermal cells as shown in Figure 2a.…”

Section: D Stack Thermal Modelmentioning

confidence: 99%

Through Silicon Via-based Grid for Thermal Control in 3D Chips

Ayala¹,

Sridhar²,

Pangracious³

et al. 2012

Design Technology for Heterogeneous Embedded Systems

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Abstract. 3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communication is the 3D integration technology and the use of through-silicon vias (TSVs) for inter-layer communication. However, 3D chips present important ther-mal issues due to the presence of processing units with a high power density, which are not homogeneously distributed in the stack. Also, the presence of hot-spots creates thermal gradients that impact negatively on the system reliability and relate with the leakage power consumption. Thus, new approaches for thermal control of 3D chips are in great need. This paper discusses the use of a grid and non-uniform placement of TSVs as an effective mechanism for thermal balancing and control in 3D chips. We have modelled the material layers and TSVs mathematically using a detailed calibration phase based on a real 5-tier 3D chip stack, where several heaters and sensors are manufactured to study the heat diffusion. The obtained results show interesting conclusions about thermal dissipation for 3D chips with TSVs and outline new insights in the area of thermal modeling and optimization for 3D chips by exploiting the inclusion of minimal percentages of TSVs in strategic positions of the layout.

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Section: D Stack Thermal Modelmentioning

confidence: 99%

Through Silicon Via-based Grid for Thermal Control in 3D Chips

Ayala¹,

Sridhar²,

Pangracious³

et al. 2012

Design Technology for Heterogeneous Embedded Systems

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“…In the first case the processors can be restructured according to a cluster-based architecture, or by duplicating portions of the processor that are known to be thermal hot-spots. Functional units are duplicated in [9], with increased hardware area and cost: these units are used alternatively to reduce the stress on each single unit (e.g., an ALU or register files). Similar work has been done in [25] in which the only register file has been duplicated, and activity migration is directed toward the spare unit under dynamic thermal constraints.…”

Section: A Design-time Thermal Optimizationmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-Multi-core architectures are a promising paradigm to exploit the huge integration density reached by highperformance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM techniques.

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“…Several schemes using architecture adaptation provided DTM solutions [2,5]. Brooks, et al suggested the fetch toggling to avoid thermal limit using the stall of instruction fetching [2].…”

Section: Related Workmentioning

confidence: 99%

“…Brooks, et al suggested the fetch toggling to avoid thermal limit using the stall of instruction fetching [2]. Heo, et al transformed the fetched computation into other duplicated unit during cooling down the overheated unit [5]. However, these schemes cannot satisfy the deadline of workload in real-time.…”

Section: Related Workmentioning

confidence: 99%