Reducing Qrr in high-voltage SuperJunction MOSFETs by using the cascode configuration

Abstract

In this paper, the reverse conduction behavior of a Cascode Configuration (CC), combining a High-Voltage (HV) SuperJunction MOSFET (SJ-FET) and a Low-Voltage silicon MOSFET (LV-FET) is deeply scrutinized by means of an analytical model and experimental data. The reverse recovery charge (Qrr) of SJ-FETs in CC with LV-FETs (SJ-CCs) is investigated in this work. As a result of the study, it has been found that the proposed SJ-CC avoids or mitigates the conduction of the SJ-FET body diode during reverse conduction. As consequence, the Qrr achieved by the CC is several times lower than in the case of the standalone configuration. Moreover, the Qrr reduction achieved results in record-low Qrr for 600 V-range silicon transistors at a fixed on-resistance (RDSON).

Overcoming switching limits in silicon power MOSFETs with silicon‐based solutions

“…Another remarkable asset offered by SJ‐CC is the reduction in reverse recovery time and charge ( t RR and Q RR ) which becomes crucial for synchronous rectification. In this sense, it is demonstrated in [45] that SJ‐CC exhibits lower Q RR * R ON than fast recovery SJ‐FETs (typically implementing techniques of carrier lifetime control). This achievement is possible by having pure channel conduction in the third quadrant, when SJ‐FET gate voltage is always set at a high voltage.…”

Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

“…Moreover, it was demonstrated that the SJ-CC can outperform the SJ-FET in standalone configuration when the switching frequency is in the order of hundreds of kHz and operating under hard-switching and high-forward current conditions [14]- [15]. Differently from the aforementioned papers, this work aims to model the third quadrant operation of the SJ-CC and to propose this configuration as a method to minimize the RR effect of the SJ-FET body-diode, enabling the use of these devices for SR [16]. This paper is organized as follows.…”

Comparison of conventional and cascode drive of SiC BJTs

“…However, instead of driving a power device directly by its control electrode, it can be driven by a second lower voltage device connected in series with its reference electrode, namely the cascode arrangement. This technique has been used with silicon MOSFETs [8, 9] and also with emerging devices including the SiC JFET [10, 11] and GaN FETs [12, 13]. Since the second device only needs to have a low voltage rating, its on‐state resistance for a given die area is low and losses in it are consequently low despite it conducting the full load current.…”