Reducing rename logic complexity for high-speed and low-power front-end architectures

Sangireddy, R.

doi:10.1109/tc.2006.88

Cited by 13 publications

(6 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We arrived at this upper bound by first estimating the delay of a 64-bit, 64-entry SRAM with 12 read and four write ports using CACTI 4.2 [10]. We further corroborated this estimate by using linear technology scaling on previously published estimations for multi-ported register files [5] [9]. Speed can be improved further at the expense of energy.…”

Section: Discussionmentioning

confidence: 76%

On the latency, energy and area of checkpointed, superscalar register alias tables

Safi

Akl

Moshovos

et al. 2007

Proceedings of the 2007 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

We present two full-custom implementations of the Register Alias Table (RAT) for a 4-way superscalar dynamically-scheduled processor in a commercial 130nm CMOS technology. The implementations differ in the way they organize the embedded global checkpoints (GCs) which support speculative execution. In the first implementation, representative of early designs, the GCs are organized as shift registers. In the second implementation, representative of more recent proposals, the GCs are organized as random access buffers. We measure the impact of increasing the number of GCs on the latency, energy, and area of the RAT. The results support the importance of recent techniques that reduce the number of GCs while maintaining performance.

show abstract

Section: Discussionmentioning

confidence: 76%

On the latency, energy and area of checkpointed, superscalar register alias tables

Safi

Akl

Moshovos

et al. 2007

Proceedings of the 2007 International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

show abstract

“…5.2). Utilizing this fact, Kim et al reduced the ports of the wakeup logic and register file [40], and Sangireddy did those of the register map table [41].…”

Section: Number Of Operandsmentioning

confidence: 99%

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThe region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.

show abstract

“…Some researchers focused on the fact that all the ports of an RMT are in general not entirely utilized, and they proposed methods that reduce the number of the ports of an RMT in order to mitigate its complexity [29], [30]. These methods can reduce the number of ports proportionally to the effective use rate of the ports, but this reduction is limited.…”

Section: Related Workmentioning

confidence: 99%

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Shioya

Ando

2016

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYOut-of-order superscalar processors rename register numbers to remove false dependencies between instructions. A renaming logic for register renaming is a high-cost module in a superscalar processor, and it consumes considerable energy. A renamed trace cache (RTC) was proposed for reducing the energy consumption of a renaming logic. An RTC caches and reuses renamed operands, and thus, register renaming can be omitted on RTC hits. However, conventional RTCs suffer from several performance, energy consumption, and hardware overhead problems. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands that are short distance from producers outside traces, and solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead as compared to a conventional processor. key words: superscalar processor, register renaming, trace cache, energy efficiency

show abstract

Reducing rename logic complexity for high-speed and low-power front-end architectures

Cited by 13 publications

References 16 publications

On the latency, energy and area of checkpointed, superscalar register alias tables

On the latency, energy and area of checkpointed, superscalar register alias tables

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency

Contact Info

Product

Resources

About