Reducing solid-state drive read latency by optimizing read-retry

Park, Jisung; Kim, Myungsuk; Chun, Myoungjun; Orosa, Lois; Kim, Jihong; Mutlu, Onur

doi:10.1145/3445814.3446719

Cited by 28 publications

(5 citation statements)

References 87 publications

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“…As explained, Step 1 only streams the data structures in batches from the underlying NAND flash chips to the internal DRAM, leveraging the SSD's full internal bandwidth. Therefore, the performance of GenStore-ER can be easily scaled up by increasing the SSD's internal parallelism (e.g., by deploying more channels or using low-latency NAND flash memory [122,151,152]).…”

Section: Genstore-em For Exactly-matching Readsmentioning

confidence: 99%

“…Similar to GenStore-EM, the steps of GenStore-NM are pipelined. The performance of GenStore-NM can be easily scaled up by increasing the SSD's internal parallelism (e.g., by deploying more channels or using low-latency NAND flash memory) [122,151,152].…”

Section: Inputmentioning

confidence: 99%

“…GenStore metadata includes the mapping information of the data structures necessary for read mapping acceleration, which enables access to the data structures without the L2P mapping table of the regular FTL. In accelerator mode, where GenStore operates as an accelerator, GenStore also keeps in internal DRAM other metadata structures of the regular FTL (e.g., the page status table and block read counts [129,152]) which need to be updated during the filtering process. We carefully design GenStore to only sequentially access the underlying NAND flash chips while operating as an accelerator, so it requires only a small amount of metadata to access the stored data.…”

Section: Genstore Flash Translation Layer (Ftl)mentioning

confidence: 99%

See 2 more Smart Citations

GenStore: a high-performance in-storage processing system for genome sequence analysis

Ghiasi

Park

Mustafa

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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of read mapping processes of reads with different properties and degrees of genetic variation, we meticulously design low-cost hardware accelerators and data/computation flows inside a NAND flashbased solid-state drive (SSD). Our evaluation using a wide range of real genomic datasets shows that GenStore, when implemented in three modern NAND flash-based SSDs, significantly improves the read mapping performance of state-of-the-art software (hardware) baselines by 2.07-6.05× (1.52-3.32×) for read sets with high similarity to the reference genome and 1.45-33.63× (2.70-19.2×) for read sets with low similarity to the reference genome. CCS CONCEPTS• Computer systems organization → Special purpose systems;• Hardware → External storage.

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Section: Genstore-em For Exactly-matching Readsmentioning

confidence: 99%

Section: Inputmentioning

confidence: 99%

Section: Genstore Flash Translation Layer (Ftl)mentioning

confidence: 99%

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GenStore: a high-performance in-storage processing system for genome sequence analysis

Ghiasi

Park

Mustafa

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

Self Cite

View full text Add to dashboard Cite

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“…Realworld storage devices could have dynamic latency variations due to their complex hardware and software components (e.g., internal caching, garbage collection, error handling, multi-level cell reading, etc.) [80][81][82][83][84][85][86][87]. Second, if the fast storage is running out of free space, there might be evictions in the background from the fast storage to the slow storage.…”

Section: Introductionmentioning

confidence: 99%

Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning

Singh¹,

Rakesh²,

Park³

et al. 2022

Preprint

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Hybrid storage systems (HSS) use multiple different storage devices to provide high and scalable storage capacity at high performance. Data placement across different devices is critical to maximize the benefits of such a hybrid system. Recent research proposes various techniques that aim to accurately identify performance-critical data to place it in a "best-fit" storage device. Unfortunately, most of these techniques are rigid, which (1) limits their adaptivity to perform well for a wide range of workloads and storage device configurations, and (2) makes it difficult for designers to extend these techniques to different storage system configurations (e.g., with a different number or different types of storage devices) than the configuration they are designed for. Our goal is to design a new data placement technique for hybrid storage systems that overcomes these issues and provides: (1) adaptivity, by continuously learning from and adapting to the workload and the storage device characteristics, and (2) easy extensibility to a wide range of workloads and HSS configurations.We introduce Sibyl, the first technique that uses reinforcement learning for data placement in hybrid storage systems. Sibyl observes different features of the running workload as well as the storage devices to make system-aware data placement decisions. For every decision it makes, Sibyl receives a reward from the system that it uses to evaluate the long-term performance impact of its decision and continuously optimizes its data placement policy online.We implement Sibyl on real systems with various HSS configurations, including dual-and tri-hybrid storage systems, and extensively compare it against four previously proposed data placement techniques (both heuristic-and machine learning-based) over a wide range of workloads. Our results show that Sibyl provides 21.6%/19.9% performance improvement in a performanceoriented/cost-oriented HSS configuration compared to the best previous data placement technique. Our evaluation using an HSS configuration with three different storage devices shows that Sibyl

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“…In [23], [24], nonuniform soft sensing read reference voltage has been demonstrated to decrease latency by achieving high error correcting capability with low precision decoding mode. The authors in [25] have introduced read-retry mechanism with consecutive retry steps in a pipelined manner to reduce the read latency. Moreover, they reduced page-sensing latency with an adaptive reference voltage precharging timing based on offline profiling.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Error Recovery Flow Prediction Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation

et al. 2022

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NAND flash memory is becoming smaller and denser to have a larger storage capacity as technologies related to fine processes are developed. As a side effect of high-density integration, the memory can be vulnerable to circuit-level noise such as random telegraph noise, decreasing the reliability of the memory. Therefore, low-density parity-check code that provides multiple decoding modes is adopted in the NAND flash memory systems to have a strong error correcting capability. Conventional static error recovery flow (ERF) applies decoding modes sequentially, and read latency can increase when preceding decoding modes fail. In this paper, we consider a dynamic ERF using machine learning (ML) that predicts an optimal decoding mode guaranteeing successful decoding and minimum read latency and applies it directly to reduce read latency. Due to process variation incurred in the manufacturing of memory, memory characteristics are different by chips and it becomes difficult to apply a trained prediction model to different chips. Training the customized prediction model at each memory chip is impractical because the computational burden of training is heavy, and a large number of training data is required. Therefore, we consider ERF prediction based on reusable ML to deal with varying input and output relationships by chips due to process variation. Reusable ML methods reuse pre-trained model architecture or knowledge learned from source tasks to adapt the model to perform its task without any loss of performance in different chips. We adopt two reusable ML approaches for ERF prediction based on transfer learning and meta learning. Transfer learning method reuses the pre-trained model by reducing domain shift between a source chip and a target chip using a domain adaptation algorithm. On the other hand, meta learning method learns shared features from multiple source chips during the meta training procedure. Next, the meta-trained model reuses previously learned knowledge to fastly adapt to the different chips. Numerical results validate the advantages of the proposed methods with high prediction accuracy in multiple chips. In addition, the proposed ERF prediction based on transfer and meta learning can yield a noticeable reduction in average read latency as compared to conventional schemes.INDEX TERMS NAND flash memory system, process variation, error management, reusable machine learning, transfer learning, meta learning.

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Reducing solid-state drive read latency by optimizing read-retry

Cited by 28 publications

References 87 publications

GenStore: a high-performance in-storage processing system for genome sequence analysis

GenStore: a high-performance in-storage processing system for genome sequence analysis

Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems Using Online Reinforcement Learning

Dynamic Error Recovery Flow Prediction Based on Reusable Machine Learning for Low Latency NAND Flash Memory Under Process Variation

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