Reducing SSD access latency via NAND flash program and erase suspension

Wu, Guanying; Huang, Ping; He, Xubin

doi:10.1016/j.sysarc.2013.12.002

Cited by 32 publications

(39 citation statements)

References 21 publications

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“…The erase operation consists of sending a series of voltage pulses into the gates of all the cells in a block, until all the floating gates have been discharged [10]. All cells in the block suffer the same pulses, despite some can be "fast erased" and others need more negative pulses [11].…”

Section: B Partial Erasementioning

confidence: 99%

Multipage Read for <sc>nand</sc> Flash

Luo

Peleato

2017

IEEE Trans. Circuits Syst. II

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NAND flash memories achieve very high densities through a series connection of all the cells in a bitline. In current memories, each wordline is read independently by biasing all the other cells to act as pass transistors and sensing all the bitlines in parallel. This paper proposes a new method which reads multiple wordlines simultaneously and returns a combination of their stored information. This multi-page read method is shown to be useful for equalizing the inter-cell interference, reduce the damage caused by erase operations, and speed up the decoding of a certain class of codes.

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Section: B Partial Erasementioning

confidence: 99%

Multipage Read for <sc>nand</sc> Flash

Luo

Peleato

2017

IEEE Trans. Circuits Syst. II

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“…Under write intensive periods of an I/O workload, this variance in latency is dominated by the program-erase cycles and garbage collection (GC) activity. For example when a program/erase cycle is running in the SSD, subsequent read I/Os had to wait till it completes [12]. To understand the effects of queueing on performance variation we experimented with virtual machines with consolidated I/O workloads on GlusterFS virtual disks as back end storage.…”

Section: Motivationmentioning

confidence: 99%

Virt Cache: Managing Virtual Disk Performance Variation in Distributed File Systems for the Cloud

Arumugam

Shi

et al. 2014

2014 IEEE 6th International Conference on Cloud Computing Technology and Science

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As Applications are moved from physical servers to virtual machines sharing storage resources, they experience large variation in I/O latencies. While maintaining average performance in such virtualized environments is important to conform to service level agreements (SLA), cloud users also expect their applications to have minimum variation in tail end latencies like 90th percentile latency for predictable performance. This becomes a challenging problem as the deviation in the application's 90th percentile I/O latency from average latency under storage resource sharing (VM consolidation) can be very high. We show through experiments under VM consolidation that during peak loads this latency variation from average can be as much as 5 times compared to when the application has exclusive access to the storage devices. This variation in performance exists for both Hard drives (HDD) and Solid state drives (SSD). To minimize this large latency variation, we propose a dynamic I/O redirection and caching mechanism called VirtCache. VirtCache can pro-actively detect storage device contention at the storage server and temporarily redirect the peaking virtual disk workload to a dynamically instantiated distributed read-write cache. We have implemented our system in GlusterFS, a commonly used distributed file system deployed as a backing store in the cloud. Our system can achieve from 50% to 83% reduction in the 90th percentile latency deviation from average compared to previous work as we move from low load conditions to peak non uniform consolidated VM workloads. With our VirtCache system, Cloud providers can guarantee predictable performance for the cloud users as if their application has exclusive access to the storage resources.

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“…When the amount of reserved free blocks falls below a threshold, a garbage collection (GC) process is performed to reclaim invalidated pages by relocating valid pages and erasing victim blocks. Note that each block can only sustain a limited number of erasures, and erasure is about ten times slower than write, which is much slower than read [48]. Due to slow writes and GC operations, random writes degrade the performance and shorten the lifetime of an SSD, and thus should be reduced in flash memory [33].…”

Section: Introductionmentioning

confidence: 99%

An efficient page-level FTL to optimize address translation in flash memory

Zhou

Huang

et al. 2015

Proceedings of the Tenth European Conference on Computer Systems

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Flash-based solid state disks (SSDs) have been very popular in consumer and enterprise storage markets due to their high performance, low energy, shock resistance, and compact sizes. However, the increasing SSD capacity imposes great pressure on performing efficient logical to physical address translation in a page-level flash translation layer (FTL). Existing schemes usually employ a built-in RAM cache for storing mapping information, called the mapping cache, to speed up the address translation. Since only a fraction of the mapping table can be cached due to limited cache space, a large number of extra operations to flash memory are required for cache management and garbage collection, degrading the performance and lifetime of an SSD. In this paper, we first apply analytical models to investigate the key factors that incur extra operations. Then, we propose an efficient page-level FTL, named TPFTL, which employs two-level LRU lists to organize cached mapping entries to minimize the extra operations. Inspired by the models, we further design a workload-adaptive loading policy combined with an efficient replacement policy to increase the cache hit ratio and reduce the writebacks of replaced dirty entries. Finally, we evaluate TPFTL using extensive trace-driven simulations. Our evaluation results show that compared to the state-of-the-art FTLs, TPFTL reduces random writes caused by address translation by an average of 62% and improves the response time by up to 24%.

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Reducing SSD access latency via NAND flash program and erase suspension

Cited by 32 publications

References 21 publications

Multipage Read for <sc>nand</sc> Flash

Multipage Read for <sc>nand</sc> Flash

Virt Cache: Managing Virtual Disk Performance Variation in Distributed File Systems for the Cloud

An efficient page-level FTL to optimize address translation in flash memory

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