Reducing the cost of floating-point mantissa alignment and normalization in FPGAs

Abstract

In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemented using several rows of small multiplexers; unfortunately, multiplexerbased logic structures map poorly onto LUTs. FPGAs, meanwhile, contain a large number of multiplexers in the programmable routing network; these multiplexer are placed under static control of the FPGA's configuration bitstream. In this work, we modify some of the routing multiplexers in the intracluster routing network of a CLB in an FPGA to implement shifters for floating-point mantissa alignment and normalization; the number of CLBs required for these operations is reduced by 67%. If shifting is not required, the routing multiplexers that have been modified can be configured to operate as normal routing multiplexers, so no functionality is sacrificed. The area overhead incurred by these modifications is small, and there is no need to modify every routing multiplexer in the FPGA. Experiments show that there is no negative impact in terms of clock frequency or routability for benchmarks that do not use the dynamic multiplexers.

Accelerating FPGA debug

“…Signals used for this purpose are determined using automated selection techniques, such as those presented in Liu and Xu [2012] and Ko and Nicolici [2009]. In a proposal similar to our approach, Moctar et al [2012] reuse the local routing multiplexers present inside each FPGA logic cluster to implement the programmable shift operation in floating-point computation, freeing up valuable soft-logic resources for more efficient use elsewhere.…”

On the difficulty of pin-to-wire routing in FPGAs

“…Moctar et al [6] seek to make use of the intra-cluster routing multiplexers to implement shifters for floating point mantissa alignment. This requires signals to be routed to the multiplexer's inputs in a pre-specified order which means that there is pin-to-wire routing.…”

“…Nevertheless, pin-to-wire routing is also motivated by other applications attempting to use the plentiful multiplexers present in the FPGA's routing fabric [6] or to implement wide shallow memories using switch block configuration bits [7]. Both these applications will benefit from knowing how much pin-to-wire routing can be introduced in a netlist before the area, delay and routability of the routed netlist are significantly impacted.…”

“…In order to make use of those multiplexers (after architecturally modifying access to their selection inputs) there has to be an ability to connect to specific data inputs on the routing multiplexers from output pins of logic blocks. For example, [6] makes use of intracluster multiplexers to implement the programmable shift in floating point operations, and shows that with careful layout, the pin-to-wire routing to multiplexers within a cluster is reasonably effective. Oldridge [7] needs a similar capa-bility to gain access to the switch block configuration bits of an FPGA, and employ them as a user memory.…”