Reducing the Overhead of BCH Codes: New Double Error Correction Codes

Saiz-Adalid, Luis-J.; Gracia-Morán, Joaquín; Gil-Tomás, Daniel; Calvo, Juan Carlos; Gil-Vicente, Pedro-J.

doi:10.3390/electronics9111897

Cited by 10 publications

(6 citation statements)

References 16 publications

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“…Next, we will compare our proposal with some typical ECCs usually used in SRAMs to tolerate multiple errors. We have selected several DEC (Double Error Correction) codes, such as matrix-based CLC [22], OLS (high speed) [23], BCH (low redundancy) [24], and LRRO (Low Redundancy and Reduced Overhead) [25], an improvement of BCH; and a TEC (Triple Error Correction) code [26], named LR TEC. Both LRRO and LR TEC have been designed by our research group.…”

Section: B Comparison With Pure Eccsmentioning

confidence: 99%

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Gil-Tomás,

Saiz-Adalid,

Gracia-Morán

et al. 2024

IEEE Access

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MBU is an increasing challenge in SRAM memory, due to the chip's large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex encoding/decoding circuits, and high memory redundancy. Alternatively, radiation-hardened cell is an alternative technique that can mask single or even double node upsets in the same cell, but at the cost of increasing the overhead of the memory array. The idea of this work is to combine both techniques to take advantage of their respective strengths. To reduce redundancy and encoder/decoder overheads, SEC Hamming ECC has been chosen. About hardened cells, well-known and robust DICE cells, able to tolerate one node upset, have been used. To assess the proposed technique, we have measured the correction capability after a fault injection campaign, as well as the overhead (redundancy, area, power, and delay) of memory and encoding/decoding circuits. Results show high MBU correction coverages with an affordable overhead. For instance, for very harmful 8-bit random MBUs injected in the same memory word, more than 80% of the cases are corrected. Area overhead values of our proposal, measured with respect to double and triple error correction codes, are less than x1.45. To achieve the same correction coverage only with ECCs, redundancy, and overhead would be much higher.

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Section: B Comparison With Pure Eccsmentioning

confidence: 99%

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Gil-Tomás,

Saiz-Adalid,

Gracia-Morán

et al. 2024

IEEE Access

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“…En realidad, se trata de obtener distintas funciones lógicas a partir de los bits de síndrome. Una explicación detallada de este proceso se puede encontrar en [23]. Un aspecto a tener en cuenta es la adaptación de las capacidades de tolerancia a fallos de este ECC.…”

Section: B Diseño De Un Código De Corrección De Errores Mediante La M...unclassified

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

Gracia-Morán

Saiz-Adalid

Calvo

et al. 2021

IEEE Latin Am. Trans.

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The continuous increment in the integration scale of CMOS technology has provoked an augment in the fault rate. Particularly, a single particle hit in a storage element (such as memory or registers) can provoke a single error in a memory cell (known as Single Cell Upsets or SCU), as well as simultaneous errors in more than one memory cell (known as Multiple Cell Upsets or MCU). A common method to tolerate this type of errors is the use of Error Correction Codes (ECC). However, the addition of an ECC introduces a series of overheads: silicon area, power consumption and delay overheads of encoding and decoding circuits, as well as several extra bits added to detect and/or correct errors. An ECC can be designed focusing on different parameters: low redundancy, low delay, error coverage, etc. The design of ECC is a very active field, and ECC with different properties are continuously proposed. However, usually, these proposals only present the ECC, not showing what happens when they are included in a microprocessor. The idea of this paper is twofold. First, we present the design of an ECC whose main characteristic is its low number of code bits (low redundancy). This ECC adds 15 redundant bits to a 32-bit data word to form a (47, 32) ECC able to correct single and doble errors, and to detect triple errors. Second, we also study the overheads that this ECC introduces when added to a RISC microprocessor, comparing it with some other well-known ECC.

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“…The work improves the correct reconstruction probability using lower-bound BCH codes than RS codes. Adalid et al [19] explain the DECbased BCH codes with overhead reduction. The work reduces the overhead of 2.8 % in propagation delay, 15.7 % in Power, and 1.3 % in chip area than conventional DEC-based BCH codes.…”

Section: Introductionmentioning

confidence: 99%

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

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Reducing the Overhead of BCH Codes: New Double Error Correction Codes

Cited by 10 publications

References 16 publications

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays

Design, Implementation and Evaluation of a Low Redundant Error Correction Code

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

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