Reducing thread divergence in a GPU‐accelerated branch‐and‐bound algorithm

Chakroun, Imen; Mezmaz, Mohand-Said; Melab, Nouredine; Bendjoudi, Ahcène

doi:10.1002/cpe.2931

Cited by 42 publications

(39 citation statements)

References 17 publications

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“…In [15] the GPU is used for the bound operator in the algorithm applied to the flow shop scheduling problem. The paper discusses GPU specific details of the implementation and in experiments a speedup of up to 77.5 compared to a single core on a CPU is achieved.…”

Section: Gpu Implementation Of Linear Programming and Branch And Boundmentioning

confidence: 99%

GPU computing in discrete optimization. Part II: Survey focused on routing problems

Schulz

Hasle

Brodtkorb

et al. 2013

EURO Journal on Transportation and Logistics

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In many cases there is still a large gap between the performance of current optimization technology and the requirements of real world applications. As in the past, performance will improve through a combination of more powerful solution methods and a general performance increase of computers. These factors are not independent. Due to physical limits, hardware development no longer results in higher speed for sequential algorithms, but rather in increased parallelism. Modern commodity PCs include a multi-core CPU and at least one GPU, providing a low cost, easily accessible heterogeneous environment for high performance computing. New solution methods that combine task parallelization and stream processing are needed to fully exploit modern computer architectures and profit from future hardware developments. This paper is the second in a series of two. Part I gives a tutorial style introduction to modern PC architectures and GPU programming. Part II gives a broad survey of the literature on parallel computing in discrete optimization targeted at modern PCs, with special focus on routing problems. We assume that the reader is familiar with GPU programming, and refer the interested reader to Part I. We conclude with lessons learnt, directions for future research, and prospects.

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Section: Gpu Implementation Of Linear Programming and Branch And Boundmentioning

confidence: 99%

GPU computing in discrete optimization. Part II: Survey focused on routing problems

Schulz

Hasle

Brodtkorb

et al. 2013

EURO Journal on Transportation and Logistics

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“…In [33], a selection operator based on the best-first strategy is used until the work pool reaches a given size. Then, a selection operator based on the depth-first strategy is used.…”

Section: B Scheduling Problems 1) Branch and Boundmentioning

confidence: 99%

“…This technique permits one to provide enough work to the GPU. The evaluation of bounds that is time consuming was performed in parallel in [33]; an original technique was also proposed to avoid divergent threads in a warp resulting from conditional branches.…”

Section: B Scheduling Problems 1) Branch and Boundmentioning

confidence: 99%

Recent Advances on GPU Computing in Operations Research

Boyer

Baz

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-In the last decade, Graphics Processing Units (GPUs) have gained an increasing popularity as accelerators for High Performance Computing (HPC) applications. Recent GPUs are not only powerful graphics engines but also highly threaded parallel computing processors that can achieve sustainable speedup as compared with CPUs. In this context, researchers try to exploit the capability of this architecture to solve difficult problems in many domains in science and engineering. In this article, we present recent advances on GPU Computing in Operations Research. We focus in particular on Integer Programming and Linear Programming.

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“…For example, in [2], authors had to transform their initial data structure and modify the conditional instructions to overcome it. To reduce CPU-GPU data transfers they used a special Johnson's algorithm (as bounding operator) that accessed precomputed special matrices, defined in [3] located in shared and cache memory.…”

Section: Introductionmentioning

confidence: 99%

A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm

Daouri

Escobar

Chang

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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Branch-and-Bound (B&B) algorithms are one of the most employed techniques in optimization problems. Its complexity increases exponentially with problem size and features a challenging dynamic memory management caused by recursive processing. Most solutions focus on parallel branch evaluation in multi-core CPUs or GPUs. To the best of our knowledge, to the date, no works have employed FPGAs to implement the BB technique. In this paper, we propose a mixed hardware-software architecture to solve the Flow-Shop Scheduling Problem (FSP). We use Vivado HLS to construct a simple processing element (PE) for lower bound computation and integrate it with an ARM processor system. A Xilinx ZYNQ-7020 device is used to synthesize 10 PEs and reach an acceleration of about 5× over bare-metal execution on the same platform. In addition, we propose a pseudo-branching technique for higher computation overlapping attaining speed ups of 10.3× for a maximum problem size of 20 jobs in 20 machines.

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Reducing thread divergence in a GPU‐accelerated branch‐and‐bound algorithm

Cited by 42 publications

References 17 publications

GPU computing in discrete optimization. Part II: Survey focused on routing problems

GPU computing in discrete optimization. Part II: Survey focused on routing problems

Recent Advances on GPU Computing in Operations Research

A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm

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