Reducing Wafer Delay Time by Robot Idle Time Regulation for Single-Arm Cluster Tools

Xiong, WenQing; Pan, Chunrong; Qiao, Yan; Wu, Naiqi; Chen, MingXin; Hsieh, PinHui

doi:10.1109/tase.2020.3014078

Cited by 33 publications

(11 citation statements)

References 63 publications

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“…Additionally, it helped to reduce the delay time of a wafer. Too long wafer delay time might damage the wafer due to the high temperature or dense chemical gas concentration [33]. This could become a trigger of some faults generated in the afterward manufacturing process.…”

Section: Resultsmentioning

confidence: 99%

Sequential and Comprehensive Algorithm for Fault Detection in Semiconductor Sensors

et al. 2021

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The semiconductor manufacturing processes have been evolved to improve the yield rate. Here, we studied a sequential and comprehensive algorithm that could be used for fault detection and classification (FDC) of the semiconductor chips. A statistical process control (SPC) method is employed for inspecting whether sensors used in the semiconductor manufacturing process become stable or not. When the sensors are individually stable, the algorithm conducts the relational inspection to identify the relationship between two sensors. The key factor here is the coefficient of determination (R2). If R2 is calculated as more than 0.7, their relationship is analyzed through the regression analysis, while the algorithm conducts the clustering analysis to the sensor pair with R2 less than 0.7. This analysis also provided the capability to determine whether the newly generated data are defective or defect-free. Therefore, this study is not only applied to the semiconductor manufacturing process but can also be to the various research fields where the big data are treated.

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Section: Resultsmentioning

confidence: 99%

Sequential and Comprehensive Algorithm for Fault Detection in Semiconductor Sensors

et al. 2021

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“…Notice that, under a PVS, the wafer type sequence to be processed by a PM at Step i is periodically repeated, and the number of wafers in such a sequence is k i obtained by Equation (6). Then, three consecutive wafer processing sequence are named as WPS-1, WPS-2, and WPS-3, respectively.…”

Section: Solution Encoding and Modificationmentioning

confidence: 99%

“…To reduce the wafer delay time for DACTs, a modified swap strategy is proposed in [5] such that a wafer waits on the robot for some time during a swap operation. For SACTs, the wafer delay time at a step can be reduced by delaying the time point of unloading a wafer at the previous step, so that the time point of loading the wafer at the step is delayed [1,6]. Feedback control methods are proposed in [7,8] to control wafer delays such that a feasible schedule can be found for both SACTs and DACTs.…”

Section: Introductionmentioning

confidence: 99%

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Scheduling of Single-Arm Cluster Tools with Residency Time Constraints and Chamber Cleaning Operations

Qiao

Zhang

et al. 2021

Applied Sciences

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To ensure wafer quality, engineers have to impose wafer residency time constraints and chamber cleaning operations on cluster tools; this has been widely used in semiconductor manufacturing. Wafer residency time constraints and chamber cleaning operations make the scheduling problem of cluster tools more challenging. This work aims to solve such a scheduling problem for single-arm cluster tools and presents a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for single-arm cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a process module (PM) processes virtual wafers, a chamber cleaning operation is performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. With this idea, this work constructs a genetic algorithm to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has high practical value to numerous semiconductor manufacturers. Experiments were performed to show the efficiency and effectiveness of the proposed method.

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“…Yang et al [7] provide a general framework to find the optimal schedule for the time-constrained SACT within both process-and transport-bound regions. In order to reduce quality variability in wafer fabrication and guarantee high-quality output, Zhu et al [9], [52] and Xiong et al [10] propose efficient methodologies to regulate robot waiting times for reducing the wafer delay time in each process step. Due to exceptional events, such as processing delay, communication delay, or wafer alignment failure, the activity time is practically subject to random variation [2].…”

Section: Introductionmentioning

confidence: 99%

Transient Process Optimization for Dual-Arm Cluster Tools With Wafer Revisiting

Wang

Pan

et al. 2021

IEEE Access

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In wafer fabrication, it is imperative to minimize the transient process of cluster tools for the sake of on-demand and preventive maintenance. Due to the trend of multi-type and small-batch production, transient processes appear more and more frequently. Thus, the optimization problems of transient processes have gained increasing attention from both industry and academia. The requirement for wafer revisiting tend to complicate this problem significantly. However, only a few studies take such a challenge for cluster tools with wafer revisiting. This paper focuses on the schedule optimization of transient processes for dual-arm cluster tools with wafer revisiting. To accelerate transient processes, including both start-up and close-down ones, we adopt a program evaluation and review technique to analyze and harness a cluster tool's state evolution. We then propose computationally efficient algorithms to speed up transient processes. Finally, we provide illustrative examples to show their applications and validate their effectiveness.INDEX TERMS Cluster tool, semiconductor manufacturing, wafer fabrication, scheduling, transient process, wafer revisiting.{0}. PM Process module. SACT Single-arm cluster tool. DACT Dual-arm cluster tool. ALD Atomic layer deposition. WRP Wafer revisiting process. k-WRP k-time Wafer revisiting process. 1-WCS One-wafer cyclic scheduling. 3-WCS Three-wafer cyclic scheduling. VWM Virtual wafer method. SUTP Start-up transient process. CDTP Close-down transient process. PERT Program evaluation and review technique.

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Reducing Wafer Delay Time by Robot Idle Time Regulation for Single-Arm Cluster Tools

Cited by 33 publications

References 63 publications

Sequential and Comprehensive Algorithm for Fault Detection in Semiconductor Sensors

Sequential and Comprehensive Algorithm for Fault Detection in Semiconductor Sensors

Scheduling of Single-Arm Cluster Tools with Residency Time Constraints and Chamber Cleaning Operations

Transient Process Optimization for Dual-Arm Cluster Tools With Wafer Revisiting

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