Reducing write amplification in flash by death-time prediction of logical block addresses

Abstract

Flash-based solid state drives lack support for in-place updates, and hence deploy a flash translation layer to absorb the writes. For this purpose, SSDs implement a log-structured storage system introducing garbage collection and writeamplification overheads. In this paper, we present a machine learning based approach for reducing write amplification in log structured file systems via death-time prediction of logical block addresses. We define death-time of a data element as the number of I/O writes before which the data element is overwritten. We leverage the sequential nature of I/O accesses to train lightweight, yet powerful, temporal convolutional network (TCN) based models to predict deathtimes of logical blocks in SSDs. We leverage the predicted death-times in designing ML-DT , a near-optimal data placement technique that minimizes write amplification (WA) in log structured storage systems. We compare our approach with three state-of-the-art data placement schemes and show that ML-DT achieves the lowest WA by utilizing the learnt I/O death-time patterns from real-world storage workloads. Our proposed approach results in up to 14% reduction in write amplification compared to the best baseline technique. Additionally, we present a mapping learning technique to test the applicability of our approach to new or unseen workloads and present a hyper-parameter sensitive study.

Challenges and future directions for energy, latency, and lifetime improvements in NVMs

“…So, in PCMs, there are two main operations: SET operation and RESET operation. These operations are controlled by electrical current as follows: while in the RESET operation High-power are used to place the memory cell into the high-resistance RESET state, for the SET ReRAM [8-11, 17, 18, 29, 66, 72, 75, 76] STT-RAM [8,[11][12][13][14][31][32][33] [ 41,42,63,65,70,73] NAND Flash [15,16,28,37,45,46,49] [ 51,54,56,61,64] 3D XPoint [25-27, 38, 40, 43, 44, 47, 48, 50] [ 51, 52, 55, 57-60, 62, 69] operation, moderate power but longer duration pulses are used to return the cell to the low-resistance SET state. Although PCM scales well and has write endurance comparable to that of NAND Flash (10 8 -10 9 ), which makes it a viable alternate for future high-speed storage devices.…”