Reduction in Gap State Density near Valence Band Edge at Al₂O₃/p‐type GaN Interface by Photoelectrochemical Etching and Subsequent SiO₂ Cap Annealing

Abstract

The process‐dependent properties of Al2O3/p‐type GaN (p‐GaN) interfaces formed by atomic layer deposition at 300 °C after photoelectrochemical (PEC) etching are reported. For investigating the gap states at the Al2O3/p‐GaN interface, metal‐oxide‐semiconductor (MOS) diodes are fabricated and examined by sub‐bandgap‐light‐assisted and temperature‐dependent capacitance–voltage (C–V) measurements. PEC etching prior to Al2O3/p‐GaN interface formation is conducted with the etching depth varied in the range between 12.5 and 32.1 nm. The C–V characteristics of the MOS diodes without PEC etching indicate Fermi‐level pinning due to the near‐surface defect level in p‐GaN at 0.7 eV above the valence band edge EV and a high density of gap states around the midgap. However, all samples with PEC etching exhibit C–V characteristics, indicating a reduction in the density of the defect states at EV + 0.7 eV and midgap states. Still, PEC etching after capless annealing at 800 °C for the activation of Mg acceptors cannot reduce the density of gap states near the valence band edge. On the other hand, annealing of a sample with a SiO2 cap layer at 800 °C after PEC etching can reduce the gap state density near the valence band edge.

Impacts of post-deposition annealing on hole trap generation at SiO2/p-type GaN MOS interfaces

“…20,21) In contrast to the low electron trap density near E C , however, GaN MOSFETs have a severe reliability issue caused by highdensity hole traps near the valence band edge (E V ). The hole trap density is so high that p-type GaN MOS capacitors typically exhibit insufficient hole accumulation, [22][23][24][25] and the threshold voltage of MOSFETs is largely shifted during switching operations. Therefore, reducing hole traps by elucidating their origin is critical for highly reliable GaN MOSFETs.…”