Reduction in power consumption of packet counter on VIRTEX-6 FPGA by frequency scaling

Abstract

In Today's World it is very easy to share the information fast may be within seconds or even may be less. However, the required data is shared so it is the main concern. We share data over web and data is transferred in the form of packets. How these data packets are transmitted is all concept of Networking. This paper focuses on making of a packet counter that consumes least power for its operation. Packet counters are used for counting data packets at transmitter and receiver end and hence finding the number of packets or data lost in whole process. The Design is implemented for LVCOMS_25, LVDCI_25, SSTL_15 and HSTL_III I/O standards for Virtex6 Field Programmable Gate Array. Percentage Change in power consumed is calculated by scaling frequency and hence efficient packet counter is achieved.