Reduction of CMP-induced wafer defects through in-situ removal of process debris

Reduction of annealed-induced wafer defects in dual-damascene copper interconnects

“…The results shown in Fig. 2a indicate that high stress in the He in situ anneal occurred because of the faster ramp rate during the annealing process, resulting in stress-induced damage, such as voids or grooves [4][5][6]. Meanwhile, the high reflectivity observed in furnace-annealed samples is due to different grain size as shown in Fig. 2b [1].…”

“…A seed layer with poor step coverage can aggravate the formation of voids during the process of gap filling [3][4][5]. In order to ascertain a smooth and continuous surface morphology of the seed, pre-stress measurement of seed layer was studied before the plating process.…”

“…The result indicates that the number of gouges is different for both anneals and differs in higher counts for three particular slots that underwent furnace anneal system. This could be due to the type of slurry used, in particular the abrasive particles employed since scratching is predominantly a mechanical wear phenomenon [4][5][6]. Fig.…”

“…For copper dual-damascene interconnects two main EM failure modes have been identified, namely the later (strong) mode and the early (weak) mode [1,4]. The later mode is dominated by void growth, while the early mode is governed by combination of both void nucleation and subsequent morphological evolution due to thermomechanical stresses induced during cooling after the thermal annealing [1,2,[4][5][6].…”

Scratch formation and its mechanism in chemical mechanical planarization (CMP)

“…It was found that the interaction between abrasive particle and polyurethane pad under tribo-mechanical action could change the pad surface hardness. Benner et al [77] used a vacuum cleaner to remove the pad debris and agglomerated large particles from the pad; they dubbed this process the pad surface manager (PSM). Figure 30 contains a plot of light-point defects measured using a Tencor 6220 on polished oxide wafers using different levels of PSM vacuum.…”