semiconductor counterpart due to large density of states, 3D electric fi eld enhancement, and selectable work function. [ 1,[3][4][5][6] Considerable work has focused on the controlled synthesis of metallic NCs for use in NVM devices. Although a wide range of metal nanocrystals have been utilized to realize functioning NVM, the lack of control over the embedded NP size, interparticle distance (areal density) makes it diffi cult to investigate the electron/hole charging characteristics as a function of embedded nanocrystal properties. To achieve the desired metal NP embedded layer for NVM applications, a CMOS compatible tilted target sputtering (TTS) technique has been previously developed [ 7 ] and is employed in this study to achieve nanoparticles (NPs) with controllable sizes, areal densities, and narrow size distributions. Using the TTS technique, the average size of the NPs can be effectively controlled by varying the deposition time with constant pressure, power, and gas fl ow rate at room temperature. [ 7,8 ] This technique has been shown to produce uniformly distributed spherical Pt NPs with mean diameters between 0.5 and 2 nm, and for certain process parameters, high areal densities as large as 10 13 cm −2 . Although embedding these Pt NPs in Al 2 O 3 has resulted in NVM devices displaying large memory windows and excellent retention characteristics, [ 5,6 ] a systematic study analyzing the effect of the deposited Pt NP size, areal density, and surface coverage on the quality/magnitude of introduced trap within the surrounding dielectric has not been reported yet. In this study, the infl uence of TTS sputtered Pt NP size, areal density, and surface coverage on the charging/discharging characteristics of Pt NP embedded NVM MOS capacitors has been explored. Three different Pt Np size domains (0.7, 0.9, and 1.6 nm) and two different areal density domains (≈5 × 10 12 cm −2 and ≈10 × 10 12 cm −2 ) were explored under the realms of this study utilizing variable frequency and scan rate dependent capacitance-voltage ( C -V ) and conductance-voltage ( G -V ) measurements. The observed experimental anomalous features within the C -V and G -V signatures have been correlated to the infl uence of different types Metal nanocrystal embedded nonvolatile memory (NVM) devices have attracted signifi cant attention over the past two decades as promising alternatives to conventional fl oating gate memory devices. This study explores the applicability of sub-2 nm Pt nanoparticle (NP) embedded in ALD Al 2 O 3 as charge storage nodes in Si-based NVM devices. The infl uence of Pt NPinduced border traps within Al 2 O 3 near the Si surface and their surface coverage dependent pinning of Pt NP work function are explored as part of this study. The pinning of the nanocrystal memories induced by a high density of dangling bonds near the Pt NP/Al 2 O 3 interface skews the expected charging/ discharging characteristics with electron programming favored over holes. The degree of this pinning has been probed utilizing C -V measurements and...