Reduction of Kink Effect of Poly-Si TFT With Bottom Field Plate by Dispersing Current Density Technique

Kang, Tsung-Kuei; Chen, Yuhan; Chien, Feng-Tso; Lin, Chun–Chi; Wang, Fang-Hsing; Liu, Han–Wen

doi:10.1109/ted.2016.2563662

Cited by 6 publications

(2 citation statements)

References 17 publications

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“…[1][2][3][4][5][6] Compared with amorphous silicon TFTs, LTPS TFTs have demonstrated higher mobility, [7][8][9] which could be further improved by adopting advanced fabrication techniques such as the use of a high-k material, patterning, and various structures. [10][11][12][13][14][15][16][17][18] However, as TFTs have been scaled down, the adverse effects of the inherent grain boundary (GB) on electrical characteristics and their reliability have become significant. [19][20][21][22] To mitigate GB effects in polycrystalline silicon (poly-Si) channel TFTs, several methods such as plasma treatment, control of grain growth direction, and adjustment of GB location in poly-Si channels have been proposed.…”

Section: Introductionmentioning

confidence: 99%

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Lee

Jin

et al. 2018

Jpn. J. Appl. Phys.

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The effects of geometrical parameters on the electrical characteristics of network-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were investigated. The grain boundary and interface trap densities were also extracted using parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (AF). It was found that the electrical characteristics were largely dependent on AF, mainly owing to reduced trap densities. However, excessive hole formation in the network-channel structure was found to increase channel resistance and decrease drain current. These results suggest that, for a given footprint device area, denser hole patterns are preferred for achieving better electrical characteristics in novel network-channel LTPS TFTs.

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Section: Introductionmentioning

confidence: 99%

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Lee

Jin

et al. 2018

Jpn. J. Appl. Phys.

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“…Numerous structural improvements have been proposed to supress kink effect, including: field plates [ 35,36 ] ; lightly doped drain (LDD) [ 37 ] ; gate overlapped LDD (GOLDD) [ 38,39 ] ; asymmetric fingered polysilicon [ 31 ] ; and extended LDD. [ 16 ] Aside from such optimizations, contact‐controlled architectures, such as the source‐gated transistor [ 40–42 ] (SGT, Figure 1b,c, Supporting Information), have the ability to supress the kink effect when designed correctly.…”

Section: Introductionmentioning

confidence: 99%

Suppression of Hot‐Carrier Effects Facilitated by the Multimodal Thin‐Film Transistor Architecture

Bestelink

Sagazan

Motte

et al. 2021

Adv Elect Materials

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Hot‐carrier effects are a persistent challenge for Ohmic contact, high carrier mobility thin‐film transistors. As semiconductor properties are systematically improved, such phenomena (e.g., the kink effect) are becoming apparent even in materials such as InGaZnO. Few of the past solutions are practical in these low‐complexity semiconductor systems. Here, it is shown that contact‐controlled devices offer robust performance under extreme biasing conditions due to their distinctive charge injection processes. The recently‐developed multimodal transistor (MMT) provides further control still, by separate regulation of current flow and magnitude. Internal electric field distributions in the source and drain regions are studied via technology computer‐aided design simulations, and support the formulation of operational guidelines for the MMT's channel control gate for optimal characteristics in saturation. As MMT principles are universal, these findings should inform device design and operation in all high carrier mobility material systems.

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Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs to Improve Gray Level Control in Low Power AMOLED Displays

Huang

Fan

et al. 2019

IEEE J. Electron Devices Soc.

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With development of high efficiency organic light emitting diodes (OLEDs), and high mobility polycrystalline silicon (poly-Si) thin-film transistors (TFTs), low power and high resolution active matrix OLED (AMOLED) displays are becoming popular for mobile applications. However, they suffer from poor control of lower gray levels, with the driving TFT being operated in the subthreshold regime. In this paper, with help of non-ideal drain-bias dependent electrical characteristics of poly-Si TFTs, operation of the driving TFT can be moved out from the subthreshold regime to allow better control of the gray levels. As a result, a dynamic voltage scaling (DVS) method is developed, and shown to be able to improve the luminous uniformity for better image quality, while effectively reducing the static power consumption.INDEX TERMS Thin-film transistor, polycrystalline silicon (poly-Si), active matrix organic light emitting diode (AMOLED), low power.XINGHUA XU received the B.S. degree in engineering and the B.S. degree in economics from Xi'an Jiao Tong University in 2016. He is currently pursuing the M.S. degree with Shanghai Jiao Tong University. His current research interest includes AMOLED display driving.

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Reduction of Kink Effect of Poly-Si TFT With Bottom Field Plate by Dispersing Current Density Technique

Cited by 6 publications

References 17 publications

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

Suppression of Hot‐Carrier Effects Facilitated by the Multimodal Thin‐Film Transistor Architecture

Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs to Improve Gray Level Control in Low Power AMOLED Displays

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