Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips

Bhowmik, Subrata; Deb, Debajit; Pradhan, Sambhu Nath; Bhattacharyya, Biswajit

doi:10.1109/tcpmt.2016.2562143

Cited by 14 publications

(1 citation statement)

References 26 publications

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“…Hence, the work of IBM researchers [25] was carried forward in [27] and their VFC architecture was redesigned to develop a tuning range from 250 MHz to 2GHz with only the involvement of components like flip-flop-based frequency dividers, multiplexers and simple decision circuits. In fact, while checking the performance of this VFC to drive a sequential core, it was found that the peak position of the current drawn inside the core is attained after 40 clock cycles, which is otherwise noted only after 10 clock cycles when steered by the conventional system clock.…”

Section: Probable Solution To Reduce the On-chip Power Supply Noisementioning

confidence: 99%

Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges

Bhattacharjee¹,

Rana²,

Majumder³

2020

Recent Trends in Communication Networks

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The on-chip activities of any modern IC are always inhibited due to the occurrence of power supply noise (PSN) in the chip power line. From many decades, researchers are pondering on what are the major issue of this PSN occurrence and how it can be suppressed without interfering the actual chip functioning. In the course of time, it is found that the uncontrolled triggering of the on-chip system clock and the unguarded on-chip power line is instigating the two major factors for the occurrence of PSN i.e., i(t) → instantaneous current and di/dt → current ramp or the rate of change of current over time. Both i(t) and di/dt are also the sub-factors to rise the PSN components like resistive noise and inductive noise respectively. In this chapter, we light upon the occurrence of resistive and inductive noise as well as depict their individual impact on the PSN occurrences. There is also discussion on how PSN is suppressed over the years in spite of facing challenges in the execution of suppression techniques. This chapter even concludes on the suitable ways for mitigating PSN in the contemporary era of delivering complex on-chip features.

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Section: Probable Solution To Reduce the On-chip Power Supply Noisementioning

confidence: 99%