IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society 2013
DOI: 10.1109/iecon.2013.6700434
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Reduction of positive feedback gain on Anti-islanding method based on frequency

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(2 citation statements)
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“…Owing to the high sampling and switching frequency, the delay block can be disregarded in the phase-locked loop (PLL) closed-loop transfer function, which reduces the third-order system to the canonical form of second order, as shown in the following equation [13][14][15]…”
Section: Synchronisation Algorithmmentioning
confidence: 99%
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“…Owing to the high sampling and switching frequency, the delay block can be disregarded in the phase-locked loop (PLL) closed-loop transfer function, which reduces the third-order system to the canonical form of second order, as shown in the following equation [13][14][15]…”
Section: Synchronisation Algorithmmentioning
confidence: 99%
“…Owing to the high sampling and switching frequency, the delay block can be disregarded in the phase‐locked loop (PLL) closed‐loop transfer function, which reduces the third‐order system to the canonical form of second order, as shown in the following equation [13–15] Hclfalse(sfalse)=kp_plls+ki_plls2+kp_plls+ki_pll=2ξωns+ωn2s2+2ξωns+ωn2 The PI gains used to determine the PLL dynamics are obtained by comparing the canonical equation with the closed‐loop transfer function, which is verified by the following equations kp_pll=2ξωn ki_pll=ωn2 Table 3 shows the parameters for the PLL controller.…”
Section: System Under Study – Control Strategymentioning
confidence: 99%