Reduction of Random Dopant Fluctuation-induced Variation in Junctionless FinFETs via Negative Capacitance Effect

doi:10.33180/infmidem2021.405

Cited by 1 publication

(1 citation statement)

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“…Several studies have been conducted to date to increase the performance of NC-based FETs and FinFETs, respectively. The incorporation of device engineering approaches, such as work function variability [8,9], material-structure evaluation [8,9], and spacer engineering [10][11][12][13], among others, has been published in recent years. However, the use of such variable permittivity spacers lowers the carrier mobility through the trap formation caused by Coulombic scattering [14] and affects circuit delays due to the increased fringe capacitance [15].…”

Section: Introductionmentioning

confidence: 99%

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Chauhan

Samajdar

2023

J. Phys. D: Appl. Phys.

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Negative Capacitance Fin field-effect transistor (NC-FinFET), due to its superior gate electrostatics and dominance over the short channel effects (SCEs), has been the key technology over the conventional devices. However, the improved device performance in terms of the various engineering practices, have paved the pathway for the advancement of NC-FinFETs. In the following work, we have proposed a novel buried oxide strategy for the NC-FinFET architecture, in which we have altered the depth of the Interfacial gate oxide (IGO) layer inside the channel and analyzed the performance characteristics using TCAD Sentaurus. Initially, we have varied the IGO thickness that is going to be buried inside the channel and performed a comparative analysis between the DC, mixed-mode and SCE parameters for the various buried configurations of the proposed NC-FinFET, in order to realize the optimized depth. We have also presented the tolerable degradation in the circuit characteristics that occurs with the varying BIGO depth. Lastly, it can be inferred from the presented interface trap discussion that the idea of buried IGO thickness holds well for the low-power electronics.

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