Reduction of the Weight-Decay Rate of Volatile Memory Synapses in an Analog Hardware Neural Network for Accurate and Scalable On-Chip Learning

A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning

“…As a result, we here report very low energy dissipation for on-chip learning in a crossbar array of VM synapses when compared to a crossbar array of a more popular NVM synapse like the Resistive Random Access Memory (RRAM) synapse [2], [3], [10], [11]. In this paper, the area footprint per VMSC has also been reduced further compared to Sharda et al [16] by eliminating the extra 1.6 fF capacitor altogether and relying only on the gate-to-source capacitance of the conventional MOSFET synapse for weight storage (C GS in Fig. 1(a)).…”

“…Based on the linearity of I D vs V DS in Fig. 1(b), if we consider V DS as the input to the synapse and G DS proportional to the synaptic weight, then the drain current I D can be considered as the output since it is proportional to the product of the input and the weight, as we expect for a NN [15], [16]. Thus, a crossbar array of such transistor synapses in Fig.…”

“…But recently, in [16], Sharda et al have optimized the peripheral transistors associated with each VM synapse for its weight modulation (what they call the Volatile Memory Synapse Cell or VMSC) such that the capacitance needed in parallel with the conventional silicon transistor (together they act as the VM synapse) is 3 orders lower (only 1.6 fF) than that in [14]. But the peripheral-transistor-circuit in [16] dissipates a lot of power/ energy because there always exists a path for current flow between the two supply lines of the VMSC.…”

“…In this paper, we propose a new VMSC design which tackles the power dissipation issue faced by Sharda et al [16]. The MOSFET synapse in our designed VMSC store nearly analog values of weight like in any other proposed crossbar [2]- [4], [16].…”

“…In this paper, we propose a new VMSC design which tackles the power dissipation issue faced by Sharda et al [16]. The MOSFET synapse in our designed VMSC store nearly analog values of weight like in any other proposed crossbar [2]- [4], [16]. But here, we have modified the NN-training algorithm such that the weight update is quantized and is limited to two bits only.…”