In Very-Large-Scale-Integration (VLSI) designs, thorough testing is indispensable for identifying the structural defects of the chip. Timely detection and correcting serious defects are pivotal in preventing faulty chips from reaching customers and avoiding failures. In scan designs, the toggling activity is a critical factor due to the defects between lower cells and metal layers, exacerbated by diverse Process, Voltage, and Temperature (PVT) conditions. These defects significantly impact design testability, quality, and reliability, necessitating meticulous testing to ensure that chips meet the desired specifications. Effectively managing power consumption in the current VLSI landscape is crucial amid the ongoing energy crisis. Balancing the need for Low-Power (LP) with the complexity of integrating transistors onto a single silicon substrate poses significant challenges. As chip densities increase, power dissipation during testing surges, adversely affecting durability, performance, cost, and reliability. Engineers are racing to optimize test power usage, employing advanced Design for Test (DFT) techniques to incorporate efficient power management into Silicon-on-Chip (SoC) designs. Linear Feedback Shift Registers (LFSRs) are phenomenal in addressing DFT parameters like power, and performance, and for better pseudo-random pattern generation. Hence, this paper proposes a groundbreaking approach to power reduction techniques deploying the LFSR architecture, and thus challenging conventional scan-based testing methods. The proposed LFSR architecture is meticulously designed and rigorously tested using Cadence DFT Modus solution on ISCAS’89 benchmarking circuits. Coverage was unequivocally evaluated for Quality of Results (QoR) metrics, such as fault coverage, memory usage, pattern counts, switching activity, fault testing, and runtime. The specific evaluation clearly proved the superiority of the LFSR-based approach over the scan-based architecture. Adopting the novel LFSR architecture resulted in a ~5.6X reduction in toggling activity accompanied by a substantial ~10K pattern reduction and a runtime of nearly ~1.5 hours. Notably, the test power was reduced to 50% showcasing superior efficiency. This approach emerges as the ideal solution for industrial designs providing the best QoR for power, performance, and area. This innovative methodology marks a significant leap toward an energy-efficient and cost-effective VLSI circuit especially for stacked 2.5-3D ICs and chiplets poised to revolutionize chip manufacturing.
