2009
DOI: 10.1007/978-3-642-00904-4_13
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Reexecution and Selective Reuse in Checkpoint Processors

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Cited by 4 publications
(5 citation statements)
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“…We used SimpleScalar [Burger and Austin 1997] for performance simulation. We modified its sim-outorder model to implement checkpoints; variable length pipelines; variable size register files; instruction queues (IQ); a stateof-the-art branch predictor (TAGE [Seznec and Michaud 2006]); a mechanism that completely hides the rollback penalty, regardless of the state of the pipeline (CRB [Golander and Weiss 2008]); and a method to reuse the outcome of branches, achieving near-perfect prediction during re-execution (RbckBr [Golander and Weiss 2007]). The simulation parameters of the baseline microarchitecture (refer to Table I) mostly follow the parameters of Power5 [Kalla et al 2004].…”
Section: Experimental Methodologymentioning
confidence: 99%
“…We used SimpleScalar [Burger and Austin 1997] for performance simulation. We modified its sim-outorder model to implement checkpoints; variable length pipelines; variable size register files; instruction queues (IQ); a stateof-the-art branch predictor (TAGE [Seznec and Michaud 2006]); a mechanism that completely hides the rollback penalty, regardless of the state of the pipeline (CRB [Golander and Weiss 2008]); and a method to reuse the outcome of branches, achieving near-perfect prediction during re-execution (RbckBr [Golander and Weiss 2007]). The simulation parameters of the baseline microarchitecture (refer to Table I) mostly follow the parameters of Power5 [Kalla et al 2004].…”
Section: Experimental Methodologymentioning
confidence: 99%
“…Hardware approaches have been used to reuse results of long-latency alu operations [7,8,9,10,11] and compress functions or arbitrary sequences of instructions into a single memoized result [12,7,8,13,14,15,16,17,18]. Further studies were performed to analyze the effectiveness and propose solutions for instruction reuse in the hardware [19,20,21,22,23,24,25,26,27].…”
Section: Related Workmentioning
confidence: 99%
“…The memo table is accessed in parallel with the first computation cycle, and the computation halts in the case of hit. Thus, memoing reduces a multi-cycle operation to one-cycle when there is a hit in the memo Golander and Weiss present in [Gol07] different instruction reuse methods for Checkpoint Processors. In checkpoint microarchitectures a misspeculation initiates the rollback, in which the latest safe checkpoint preceding the point of misprediction is recovered, and the reexecution of the entire code segment between the recovered checkpoint and the mispredicting instruction (selective reissue).…”
Section: Related Workmentioning
confidence: 99%
“…We considered the following operations: V*0, V*1, 0/V, V/1 and V/V. A simple hardware scheme for detecting trivial computations and selecting the result is presented in [Gol07] and consists in comparators for the input operands and selectors for the write-back. If during the dispatch stage, a MUL instruction is detected with an operand value of 0 or 1, the result is provided by the detector, avoiding the functional unit allocation and execution.…”
Section: Selective Dynamic Instruction Reusementioning
confidence: 99%