Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

Chen, Shih En; Lin, Jzau-Sheng; Li, Hsin Fang; Cheng, Kuang Wei

doi:10.1049/iet-cds.2019.0195

Cited by 2 publications

(4 citation statements)

References 17 publications

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“…Therefore, we do not comment further on this point. −59.8 (3) (4) −52.3 (3) (4) −50 (3) −76 (3) −79.1 (3) −68 (5) Normalized sensitivity (6) (dB) −74.8 (4) −67.3 (4) −76.5 −87.5 −89.1 −80 FoM (7) ( 1) Computed assuming 1% activity of reception [15]. (2) Input matching network (IMN) gains of this paper are estimated through simulations.…”

Section: Discussionmentioning

confidence: 99%

“…However, PLLs need long preamble times (tens of bit times) to settle the clock frequency according to the received data rate, which is not acceptable in the case where the WuRx must also be employed for burst communications. A WuRx with an injection-locked oscillator (ILO) CDR, which guarantees lower preamble times, was proposed in [15]. Nevertheless, [15] needed Manchester encoding for the received data, which implies a halving in the data rate to prevent the ILO from going back to its free running mode due to the absence of data transitions.…”

Section: Introductionmentioning

confidence: 99%

“…A WuRx with an injection-locked oscillator (ILO) CDR, which guarantees lower preamble times, was proposed in [15]. Nevertheless, [15] needed Manchester encoding for the received data, which implies a halving in the data rate to prevent the ILO from going back to its free running mode due to the absence of data transitions. Recently, [16] proposed a wake-up and data receiver in which the sampling time selection was achieved through a digitally programmable interface, while frequency control was carried out using a frequency-locked loop (FLL).…”

Section: Introductionmentioning

confidence: 99%

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A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

et al. 2021

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This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

et al. 2021

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“…The coded preamble concept has been suggested to enhance the wake-up signal's data delivery efficiency and improve noise immunity [29]. Additionally, some designs implement external clock extraction to reduce the power consumption [5], [30], [31].…”

Section: Introductionmentioning

confidence: 99%

Tunable, Asynchronous, and Nanopower Baseband Receiver for Charging and Wakeup of IoT Devices

Benbuk

Kouzayha

Costantine

et al. 2022

IEEE Internet Things J.

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This paper proposes a novel ultra-low power, tunable, and asynchronous baseband architecture for joint radio frequency (RF) wake-up and charging receivers. The designed system switches between the wake-up and charging operations based on the type of the received RF signal. To our knowledge, the proposed system is the first of a kind that introduces multiple power states to reduce the energy consumption by sequentially activating minimal components required for RF wake-up or charging. The fabricated prototype, using off-theshelf components, features a sensitivity of -40 dBm, a bit rate of 500 bps, and a current consumption of 225 nA at a bias voltage of 2.6 V in the listening state. Current consumption is estimated at 3.225 µA and 13.725 µA while processing the preamble and bit sequence, respectively. The address detector is powered OFF during charging to reduce the system's current consumption to 150 nA. Our experimental results show that shutting down the address detector during charging reduces charging time and allows charging from received power levels that are as low as -6 dBm. We demonstrate that, operating the detector with multiple power modes reduces its current consumption and enhances its noise immunity when compared to conventional address detectors with two power modes of operation.

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Reference‐less wake‐up receiver with noise suppression and injection‐locked clock recovery

Cited by 2 publications

References 17 publications

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Tunable, Asynchronous, and Nanopower Baseband Receiver for Charging and Wakeup of IoT Devices

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