Regional Consistency: Programmability and Performance for Non-cache-coherent Systems

Abstract

Abstract-Parallel programmers face the often irreconcilable goals of programmability and performance. HPC systems use distributed memory for scalability, thereby sacrificing the programmability advantages of shared memory programming models. Furthermore, the rapid adoption of heterogeneous architectures, often with non-cache-coherent memory systems, has further increased the challenge of supporting shared memory programming models. Our primary objective is to define a memory consistency model that presents the familiar threadbased shared memory programming model, but allows good application performance on non-cache-coherent systems, including distributed memory clusters and accelerator-based systems. We propose regional consistency (RegC), a new consistency model that achieves this objective. Results on up to 256 processors for representative benchmarks demonstrate the potential of RegC in the context of our prototype distributed shared memory system.

Towards Virtual Shared Memory for Non-cache-coherent Multicore Systems

“…For performance reasons, DSM's typically weaken the consistency model in some way. We have proposed regional consistency (RegC) [4], a new memory consistency model that is nearly as strong as hardware shared memory, but allows for performant implementations on physically distributed memory systems. RegC allows existing threaded codes to run on distributed memory clusters with only trivial code modifications.…”

“…Samhita keeps the shared global address space consistent using regional consistency (RegC) [4]. The RegC consistency model has two primary goals: to enable existing shared memory code to be easily ported to Samhita with trivial code modification, and to allow for a performant implementation of the consistency model.…”