Register array-based VLSI architecture of H.265/HEVC loop filter

Abstract

A high-performance VLSI architecture for H.265/HEVC loop filter is proposed. The architecture is implemented by a parallel register array that consists of 8 × 8 registers with two data flow directions. The register array computes the sub-blocks of four different coding tree blocks at the same time based on the analysis of the computation order. This leads to the small number of registers used in the register array. The architecture computes 4 K UHD at 30 fps in realtime. The size of the synthesized design is 54 K gates. The operating clock frequency is 225 MHz in TSMC 65 nm process. If the degree of parallelism is increased to four, the architecture can compute up to 8 K UHD at 60 fps.

FPGA implementation of a HEVC deblocking filter for fast processing of super high resolution applications

“…The comparison of gate counts and clock cycles of the proposed deblocking filter with existing architectures is given in Table 2. 2 that the proposed architecture has a lower gate count than that from [9] and [10] but not [5] and [11]; however, clock cycles required by [5] and [11] are much greater than the proposed one. [10] achieved fewer clock cycles at the cost of using large size memories and higher gate count.…”

Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

“…A Convolutional Neural Network (CNN) based in-loop filter with coding unit classification is implemented in [20,21]. Among the two in-loop filters in HEVC, SAO filter alone is implemented in [22] and deblocking filter alone is implemented in [5,23,24,25,26,27,28,29]. The architecture implemented in [24] is a multi-parallel architecture built with four parallel filtering cores along with boundary judgment.…”