Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation

Abstract

Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and routers. Failures in NoC components diminish system efficiency and reliability. This paper proposes a Reinforcement Learning based Fault-Tolerant Routing (RL-FTR) algorithm to tackle the routing issues caused by link and router faults in the mesh-based NoC architecture. The efficiency of the proposed RL-FTR algorithm is examined using System-C based cycle-accurate NoC simulator. Simulations are carried out by increasing the number of links and router faults in various sizes of mesh. Followed by simulations, real-time functioning of the proposed RL-FTR algorithm is observed using the FPGA implementation. Results of the simulation and hardware shows that the proposed RL-FTR algorithm provides an optimal routing path from the source router to the destination router.

RLARA: A TSV-Aware Reinforcement Learning Assisted Fault-Tolerant Routing Algorithm for 3D Network-on-Chip

“…Some 3D NoC routing solutions use Q-learning to alleviate congestion [20] and do the thermal management [21]. Inspired by the Q-learning based fault-tolerant algorithm for 2D NoCs [25,26], we try to design a 3D NoC fault-tolerant routing algorithm RLARA. The faults are injected randomly in the horizontal links or vertical TSVs at a specific fault injection rate between different routers as is shown in Figure 1c.…”

“…Some 3D NoC routing solutions use Q-learning to alleviate congestion [20] and do the thermal management [21]. Inspired by the Q-learning based fault-tolerant algorithm for 2D NoCs [25,26], we try to design a 3D NoC fault-tolerant routing algorithm RLARA.…”