Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Reza, Farhadur; Le, Tung

doi:10.1109/iscas51556.2021.9401790

Cited by 6 publications

(6 citation statements)

References 48 publications

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“…Additionally, the proposed work is tested against the benchmarks from SPEC CPU 2006. Based on the information about traffic and congestion at the NoC, Reza and Le [11] proposes a similar routing technique which employed three RL algorithms at runtime. Power-saving methods such as power gating and the concept of dynamic voltage and frequency scaling (DVFS) were used in NoCs by Zheng and Louri [12].…”

Section: Related Workmentioning

confidence: 99%

Performance analysis of congestion-aware Q-routing algorithm for network on chip

Srivastava,

Moharir,

Gunisetty

2024

IJ-AI

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<p>A network on chip’s performance is greatly impacted by network congestion due to the substantial increase in latency and energy utilized. Designing routing strategies that keep the network informed of the status of traffic is made easier by machine learning techniques. In this work, a reinforcement-based congestion-aware Q-routing (CAQR) technique has been presented. The proposed algorithm performed better in comparison to the conventional XY routing method tested against the SPEC CPU2006 benchmark suite in the gem5 NoC simulator tool. The suite used has 4 benchmarks, namely, namd, lbm, leslie3d and bzip2 which can be used for the cores in the network in any combination. The tests were run with 16 cores on a 44 network with the maximum instruction count supported by the system (here 5,000). The proposed Q-routing algorithm showed an average of 19% reduction for benchmark simulation as compared to the Dimension-ordered (X-Y) routing for readings of average packet latency which is a crucial factor in determining a network’s efficiency. The analysis also shows an average reduction of 24%, 10%, 23% and 47% in terms of average packet network latency, average flit latency, average flit network latency and average energy consumption across various benchmarks.</p>

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Section: Related Workmentioning

confidence: 99%

Performance analysis of congestion-aware Q-routing algorithm for network on chip

Srivastava,

Moharir,

Gunisetty

2024

IJ-AI

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“…Because of this type of execution, more congestion will be aroused by diminishing the resource for routing. 15 In order to design a successful routing algorithm for NoC, some essential features are required, such as the current condition of any network, thermal awareness to diminish both permanent and temporary fault ratios, and energy-efficient path selection. 16 Also, the algorithm should adopt all the NoC topologies.…”

Section: Literature Reviewmentioning

confidence: 99%

“…The tornado traffic pattern is moved from the training set for testing purposes in the second dataset. Finally, Dataset 2 is insisted with training (17,616) and testing (15,888) samples. In Dataset 3, only the random traffic alone is used for training, and all data has been removed to test the data.…”

Section: The Svr Learning Performancementioning

confidence: 99%

“…Reza et al 15 proposed RL based routing to improve the performance of the NoC. RL suggests a routing algorithm based on learning NoC congestion and traffic.…”

Section: Literature Reviewmentioning

confidence: 99%

“…These parameters may degrade the performance of the algorithm 14 when a packet needs to travel in a particular direction because of congestion and to eliminate deadlock condition, the packet travel in the opposite direction. Because of this type of execution, more congestion will be aroused by diminishing the resource for routing 15 . In order to design a successful routing algorithm for NoC, some essential features are required, such as the current condition of any network, thermal awareness to diminish both permanent and temporary fault ratios, and energy‐efficient path selection 16 .…”

Section: Literature Reviewmentioning

confidence: 99%

See 2 more Smart Citations

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Sudhakar,

Reddy,

Penchalaiah

et al. 2023

Int J Communication

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SummaryNetwork on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning‐based latency aware predictive routing model for on‐chip networks to route packets with better performance and power efficiency. The deep learning model used in this research is a new convolutional residual gated recurrent unit (CRGRU) with queuing theory. Moreover, the source and channel queuing delay is comprised of features to learn spatial and sequential information that improves the overall prediction accuracy. This router is modified by the intrusion of the Router States Monitor unit and the CRGRU hardware engine. The work is executed using the Xilinx platform, and the performance measures like latency and throughput are obtained by varying the network size as , , and and also varying the buffer space and length as , , and , respectively. In addition, the squared correlation coefficient (SCC) and normalized root mean square error (NRMSE) are evaluated and compared with existing learning models to validate the proposed model.

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Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

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Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

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Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Cited by 6 publications

References 48 publications

Performance analysis of congestion-aware Q-routing algorithm for network on chip

Performance analysis of congestion-aware Q-routing algorithm for network on chip

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

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