Relaxation Delay of Ge‐Rich Epitaxial SiGe Films on Si(001)

Abstract

advance the present, fully group-IV-based room temperature light-emitting devices [6] or photodetectors. [7,8] For many of these applications, the Ge concentrations x for the thick but pseudomorphic Si 1-x Ge x films (TPFs) should be ideally in the range between 50% and 100%, to ensure, e.g., large enough band offsets between the Si and SiGe layers. [5,9] However, the literature reports mainly focus on TPFs with low Ge contents, x < 0.5, [10][11][12][13][14][15][16][17][18] with only a few exceptions for which the critical thickness for pronounced relaxation was evaluated for single Ge concentrations of about 55%. [11,17] In general, during the growth of strained epitaxial layers, the strain energy increases with the square of the misfit strain and linearly with the layer thickness. Thus, TPFs must release the inherent strain energy by either plastic or elastic relaxation above a misfit strain-dependent critical thickness (t c ). The former via the insertion of misfit dislocations, [19] the latter via an increase in surface energy, i.e., by forming 3D objects, such as surface undulations, quantum dots, or wires. [20] A general trend confirmed by this work is that for sufficiently high growth temperatures and beyond t c for flat film growth, lower misfits lead to the formation of dislocations (plastic relaxation), while for high misfits, typically 3D nanostructures form via elastic relaxation. [12,21,22] Along similar lines, a mixture of low-and high-temperature growth can be used to produce flat relaxed films, starting from low-temperature growth to favor dislocation insertion, followed by high-temperature growth to increase the film quality. [23][24][25] Equilibrium theory for t c of TPFs was first developed in the 70s [26,27] but did not consider that, in reality, the growth of TPFs, e.g., by molecular beam epitaxy (MBE), happens far from thermal equilibrium. Hence, the kinetic suppression of either dislocation nucleation or quantum dot formation at low growth temperatures (T G ) explains why for Ge concentrations x < 55% experimentally found values of t c exceed those predicted by equilibrium theory by about an order of magnitude. [11,17,[28][29][30] Along the same lines, it was shown that supersaturation in the wetting layer (WL) occurs before the nucleation of quantum dots or wires during the epitaxial deposition of pure Ge thin films. [31] However, at T G ¼ 700 °C, the supersaturation amounts to only %0.14 nm of Ge, and quantum dot formation occurs already after the deposition of 0.6 nm. [32] Notably, the onset of quantum dot formation can be accelerated or delayed by increasing or decreasing T G , respectively. [33,34]

Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

“…Increasing the Ge content in the Si x Ge 1 −x alloy would lead to a more dominant p‐type behavior, due to the Fermi‐level pinning close to the valence band, thus resulting in asymmetric on‐currents of the n‐ and p‐mode operation. [ 31 ] For device fabrication, a new type of ultra‐low temperature molecular beam epitaxy (MBE) of silicon‐germanium [ 32 ] enabled to grow a (100) surface oriented Si 0 . 67 Ge 0 .…”

“…Increasing the Ge content in the Si x Ge 1−x alloy would lead to a more dominant p-type behavior, due to the Fermi-level pinning close to the valence band, thus resulting in asymmetric on-currents of the n-and p-mode operation. [31] For device fabrication, a new type of ultra-low temperature molecular beam epitaxy (MBE) of silicon-germanium [32] enabled to grow a (100) surface oriented Si 0.67 Ge 0.33 layer with a thickness of d SiGe = 8 nm with high crystalline quality on top of the device layer of a silicon on insulator (SOI) substrate with a device layer of d Si = 20 nm. To cap the Si 0.67 Ge 0.33 layer, a Si layer with a thickness of d cap = 3 nm was grown atop.…”

“…Epitaxial Growth of Si 0.67 Ge 0.33 on SOI: For the growth of the Si 0.67 Ge 0.33 on SOI, recent growth strategies were adapted for the successful formation of Ge-rich but pseudomorphic 2D films with low surface roughness deposited on bulk Si substrates. [32,55] The layers were grown in a Riber SIVA-45 MBE system on SOI in (100) orientation. The BOX and device layer thickness for the SOI was 100 nm / 20 nm, respectively.…”

A Run-Time Reconfigurable Ge Field-Effect Transistor With Symmetric On-States

“…too thin for the here proposed device applications. Thereto, ultra-low temperature MBE [13] was employed to grow a (100) surface oriented Ge layer with a thickness of d Ge = 4 nm onto the device layer of a commercially available SOI wafer with a device layer of d Si = 20 nm. Importantly, for the growth of strained and defect free Ge, growth temperatures slightly below 574 K are required.…”

“…Thus, the growth of the here presented structures, while performed with MBE, can be considered as CMOS compatible. [13] Moreover, a high-resolution transmission microscopy (HRSTEM) image of the channel stack is shown in Figure 1b. To exclude the formation of instable Ge oxide throughout device fabrication, a Si capping layer with a thickness of d cap = 3 nm was gown and thermally oxidized to obtain a 5 nm to 9 nm thick SiO 2 interface dielectric layer.…”