Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors

Abstract

Reliability should be identified as the most important challenge in future nano-scale very large scale integration (VLSI) implementation technologies for the development of complex integrated systems. Normally, fault tolerance (FT) in a conventional system is achieved by increasing its redundancy, which also implies higher implementation costs and lower performance that sometimes makes it even infeasible. In contrast to custom approaches, a new class of applications is categorized in this paper, which is inherently capable of absorbing some degrees of vulnerability and providing FT based on their natural properties. Neural networks are good indicators of imprecision-tolerant applications. We have also proposed a new class of FT techniques called relaxed fault-tolerant (RFT) techniques which are developed for VLSI implementation of imprecision-tolerant applications. The main advantage of RFT techniques with respect to traditional FT solutions is that they exploit inherent FT of different applications to reduce their implementation costs while improving their performance. To show the applicability as well as the efficiency of the RFT method, the experimental results for implementation of a face-recognition computationally intensive neural network and its corresponding RFT realization are presented in this paper. The results demonstrate promising higher performance of artificial neural network VLSI solutions for complex applications in faulty nano-scale implementation environments.

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators

“…Hamid Reza Mahdiani etc. [38] proposed to relax the fault-tolerance of the VLSI implementation by employing TMR to only the computation of the most important bits such that the hardware overhead is reduced and the critical path latency is improved. Nevertheless, these approaches either require model retraining or can be sensitive to the fault distribution.…”

Automated design of error-resilient and hardware-efficient deep neural networks

“…A third approach is to use modifications in hardware that are tailored to exploit the algorithmic resilience properties of neural networks. This can be zero-biased [3] or selectively hardened [53] memory cells, optimized data representations [96], masking techniques [71,76], anomaly detectors [53,81] and relaxed versions of classical fault tolerance mechanisms, such as triple modular redundancy (TMR) [61] and algorithm-based fault tolerance (ABFT) checksums [78].…”

Approximate Arithmetic for Low-Power Image Median Filtering

“…Line buffers are used to hold the elements of columns or rows (depending on the image scan direction). Their length is determined This causes that all pixel values in each window position are processed at the same time [37]. In this case, regardless of the length of the input data, the output pixel is generated in every clock pulse.…”