Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

Bistouni, Fathollah; Jahanshahi, Mohsen

doi:10.1007/s10836-016-5601-5

Cited by 4 publications

(3 citation statements)

References 62 publications

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“…Time-dependent reliability is the probability that the system meets the requirements within the specified time within the life expectancy of the system (t > 0). In the reliability analysis of the network, there are three kinds of measures, namely terminal pair reliability, k-terminal reliability, and all-terminal reliability [ 16 ]. The terminal pair reliability of the network is defined as the probability that there is at least one fault-free path between the specified source node and the specified destination node.…”

Section: Reliability Analysismentioning

confidence: 99%

“…Dependability is an integrative concept that encompasses the following attributes: reliability, availability, safety, security, performability, maintainability, and testability [ 14 ]. Among them, researchers pay the most attention to reliability evaluation [ 15 , 16 ]. In the process of data transmission, node or link failure happens from time to time, which leads to an inability to transmit the data reliably.…”

Section: Introductionmentioning

confidence: 99%

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Design and Reliability Analysis of a Novel Redundancy Topology Architecture

Liu

Gao

et al. 2022

Sensors

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Topology architecture has a decisive influence on network reliability. In this paper, we design a novel redundancy topology and analyze the structural robustness, the number of redundant paths between two terminal nodes, and the reliability of the proposed topology by using natural connectivity and time-independent and time-dependent terminal pair reliability, k-terminal reliability, and all-terminal reliability comprehensively and quantitatively, and we compare these measures of the proposed topology with AFDX in three scenarios. The evaluations show that in the structural robustness analysis, when no nodes are removed, the natural connectivity of the proposed topology with 10 nodes, 16 nodes, and 20 nodes is 77.8%, 26.95%, and 81.39% higher than that of AFDX, respectively. In the time-independent reliability analysis, when the link reliability is 0.9, terminal pair reliability of the proposed topology with 10 nodes, 16 nodes, and 20 nodes is 5.78%, 17.75%, and 34.65% higher than that of AFDX, respectively; k-terminal reliability is 10.04%, 31.97%, and 53.74% higher than that of AFDX, respectively; and all-terminal reliability is 29.36%, 74.37%, and 107.91% higher than that of AFDX, respectively. In the time-dependent reliability analysis, when the operating time is 8000 h, the terminal pair reliability of the proposed topology with 10 nodes, 16 nodes, and 20 nodes is 3.53%, 10.87%, and 21.08% higher than that of AFDX, respectively; the k-terminal reliability is 6.20%, 19.65%, and 32.58% higher than that of AFDX, respectively; and the all-terminal reliability is 18.25%, 45.04%, and 63.86% higher than that of AFDX, respectively. The proposed topology increases the redundant paths of data transmission. It ensures reliable data transmission and has high robustness and reliability. It provides a new idea for improving the reliability of industrial buses.

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Section: Reliability Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Reliability Analysis of a Novel Redundancy Topology Architecture

Liu

Gao

et al. 2022

Sensors

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“…In this section, we take some beneficial lessons towards making research advancements in the design of efficient interconnection networks from the literature (such as [2,3,7,21,35,58,[61][62][63][64][65][66][67][68]) and open up some new directions and guidelines.…”

Section: Future Recommendationsmentioning

confidence: 99%

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

et al. 2021

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Interconnection networks provide an effective means by which components of a system such as processors and memory modules communicate to provide reliable connectivity. This facilitates the realization of a highly efficient network design suitable for computational-intensive applications. Particularly, the use of multistage interconnection networks has unique advantages as the addition of extra stages helps to improve the network performance. However, this comes with challenges and trade-offs, which motivates researchers to explore various design options and architectural models to improve on its performance. A particular class of these networks is shuffle exchange network (SEN) which involves a symmetric N-input and N-output architecture built in stages of N/2 switching elements each. This paper presents recent advances in multistage interconnection networks with emphasis on SENs while discussing pertinent issues related to its design aspects, and taking lessons from the past and current literature. To achieve this objective, applications, motivating factors, architectures, shuffle exchange networks, and some of the performance evaluation techniques as well as their merits and demerits are discussed. Then, to capture the latest research trends in this area not covered in contemporary literature, this paper reviews very recent advancements in shuffle exchange multistage interconnection networks within the last few years and provides design guidelines as well as recommendations for future consideration.

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Interconnection Networks

Jahanshahi¹,

Bistouni²

2018

Computer Communications and Networks

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A novel approach for an efficient network-on-chip using a modified Fat Tree is presented. Contention is eliminated and latency is reduced through an improved topology and router architecture. The adopted topology increases performance without a substantial increase in the routing cost. This is achieved by using an improved buffer-less, paremeterizable router architecture. The proposed router architecture is simple to implement yet can achieve the required packet collision avoidance. Simulation results that show the level of performance achieved by both the topology and the router architecture are presented. A throughput of more than 90% is achieved way above the 40-50% usually seen in other networks on chips.

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Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

Cited by 4 publications

References 62 publications

Design and Reliability Analysis of a Novel Redundancy Topology Architecture

Design and Reliability Analysis of a Novel Redundancy Topology Architecture

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

Interconnection Networks

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