Reliability analysis of NAND gates with modified channel length in series n-MOSFETs

Abstract

A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented in standard 90 nm CMOS process. Stress time tstrs dependence of degradation ratio of delay time td and operation current lop follow a power law of tstrs. A channel length modification from 0.10 to 0.11 f.!m for the topmost n-MOSFET in series connected MOSFETs of NAND gates provides not only leakage current reduction but reliability improvement with less performance degradation under high voltage stress condition.

A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress

“…Although measurements of monitoring devices fabricated on chip under DC voltage stress are widely used for reliability analysis, the evaluation of the degradation of device and circuit performance under AC stress is also imperative for CMOS digital circuit design. Conventional ring oscillator structures can be usually monitored their frequency or clone devices, but MOSFETs in the CMOS inverter itself are scarcely accessed from outside the chip [3,4].…”